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?2004 silicon storage technology, inc. s71255-00-000 3/04 1 the sst logo, superflash, and flashflex are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specifications features: ? 8-bit 8051-compatible microcontroller (mcu) with embedded superflash memory ? fully software compatible ? development toolset compatible ? pin-for-pin package compatible sst89e5xxrd2 operation ? 0 to 40 mhz at 5v sst89v5xxrd2 operation ? 0 to 33 mhz at 3v 1 kbyte internal ram dual block superflash eeprom ? 8/16/32/64 kbyte primary block + 8 kbyte secondary block (128-byte sector size for both blocks) ? individual block security lock with softlock ? concurrent operation during in-application programming (iap) ? memory overlay for interrupt support during iap support external address range up to 64 kbyte of program and data memory three high-current drive ports (16 ma each) three 16-bit timers/counters full-duplex, enhanced uart ? framing error detection ? automatic address recognition ten interrupt sources at 4 priority levels ? four external interrupt inputs programmable watchdog timer (wdt) programmable counter array (pca) four 8-bit i/o ports (32 i/o pins) and one 4-bit port second dptr register low emi mode (inhibit ale) spi serial interface standard 12 clocks per cycle, the device has an option to double the speed to 6 clocks per cycle. ttl- and cmos-compatible logic levels brown-out detection low power modes ? power-down mode with external interrupt wake-up ? idle mode temperature ranges: ? commercial (0c to +70c) ? industrial (-40c to +85c) packages available ? 44-lead plcc ? 40-pin pdip (port 4 feature not available) ? 44-lead tqfp product description the sst89e5xxrd2 and sst89v5xxrd2 are members of the flashflex51 family of 8-bit microcontroller products designed and manufactured with sst?s patented and pro- prietary superflash cmos semiconductor process tech- nology. the split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for sst?s customers. the devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontrol- ler devices. the devices come with 16/24/40/72 kbyte of on-chip flash eeprom program memory which is partitioned into 2 independent program memory blocks. the primary block 0 occupies 8/16/32/64 kbyte of internal program memory space and the secondary block 1 occupies 8 kbyte of internal program memory space. the 8-kbyte secondary block can be mapped to the lowest location of the 8/16/32/64 kbyte address space; it can also be hidden from the program counter and used as an inde- pendent eeprom-like data memory. in addition to the 16/24/40/72 kbyte of eeprom program memory on-chip, the devices can address up to 64 kbyte of external program memory. in addition to 1024 x8 bits of on-chip ram, up to 64 kbyte of external ram can be addressed. the flash memory blocks can be programmed via a stan- dard 87c5x otp eprom programmer fitted with a special adapter and the firmware for sst?s devices. during power- on reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in-application programming (iap) oper- ation. the devices are designed to be programmed in-sys- tem and in-application on the printed circuit board for maximum flexibility. the devices are pre-programmed with an example of the bootstrap loader in the memory, demon- strating the initial user program code loading or subsequent user code updating via the iap operation. the sample bootstrap loader is available for the user?s reference and convenience only; sst does not guarantee its functionality or usefulness. chip-erase or block-erase operations will erase the pre-programmed sample code. flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 sst89e/v516 / 58 / 54 / 52rd2 flashflex51 mcu
2 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table of contents product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.0 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 program flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 program memory block switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 data ram memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 expanded data ram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 dual data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0 flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1 external host programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2 in-application programming mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.0 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.1 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2 timer set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3 programmable clock-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.0 serial i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1 full-duplex, enhanced uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.0 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.0 programmable counter array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.1 pca overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2 pca timer/counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3 compare/capture modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 3 ?2004 silicon storage technology, inc. s71255-00-000 3/04 9.0 security lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1 hard lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2 softlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.3 security lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.4 read operation under lock condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.0 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.2 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.3 brown-out detection reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.0 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.1 interrupt priority and polling sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.0 power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.2 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.0 system clock and clock options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.1 clock input options and recommended capacitor values for oscillator . . . . . . . . . . . . . . . . . . . . . . 67 13.2 clock doubling option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14.0 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.2 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14.3 flash memory programming timing diagrams with external host mode . . . . . . . . . . . . . . . . . . . . . . 82 15.0 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 16.0 packaging diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 list of figures figure 2-1: pin assignments for 40-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2-2: pin assignments for 44-lead tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2-3: pin assignments for 44-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3-1: program memory organization for 8 kbyte sst89e/v52rd2. . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3-2: program memory organization for 16 kbyte sst89e/v54rd2. . . . . . . . . . . . . . . . . . . . . . . 12 figure 3-3: program memory organization for 32 kbyte sst89e/v58rd2. . . . . . . . . . . . . . . . . . . . . . . 12 figure 3-4: program memory organization for 64 kbyte sst89e/v516rd2. . . . . . . . . . . . . . . . . . . . . . 13 figure 3-5: internal and external data memory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 3-6: dual data pointer organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4-1: i/o pin assignments for external host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 figure 6-1: framing error block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 6-2: uart timings in mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 6-3: uart timings in modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 6-4: spi master-slave interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 6-5: spi transfer format with cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 6-6: spi transfer format with cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 7-1: block diagram of programmable watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 8-1: pca timer/counter and compare/capture modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 8-2: pca capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 8-3: pca compare mode (software timer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 8-4: pca high speed output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 8-5: pca pulse width modulator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 8-6: pca watchdog timer (module 4 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 9-1: security lock levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 10-1: power-on reset circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 11-1: interrupt structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 13-1: oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 14-1: i dd vs. frequency for 3v sst89v5xxrd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 14-2: i dd vs. frequency for 5v sst89e5xxrd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 14-3: external program memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 figure 14-4: external data memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 14-5: external data memory write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 14-6: external clock drive waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 14-7: shift register mode timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 14-8: ac testing input/output test waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 14-9: float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 14-10: a test load example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 14-11: i dd test condition, active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 14-12: i dd test condition, idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 14-13: i dd test condition, power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 14-14: read-id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 5 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-15: select-block1 / select-block0 (for sst89e/v516rd2 only) . . . . . . . . . . . . . . . . . . . . . . . 82 figure 14-16: chip-erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 14-17: block-erase for sst89e/v516rd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 14-18: block-erase for sst89e/v5xrd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 14-19: sector-erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 14-20: byte-program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 14-21: prog-sb1 / prog-sb2 / prog-sb3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 14-22: prog-sc0 / prog-sc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 14-23: byte-verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 list of tables table 2-1: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3-1: sfcf values for program memory block switching for sst89e/v516rd2 . . . . . . . . . . . . . 13 table 3-2: sfcf values for program memory block switching for sst89e/v5xrd2 . . . . . . . . . . . . . . 13 table 3-3: sfcf values under different reset conditions (sst89e/v5xrd2) . . . . . . . . . . . . . . . . . . . 14 table 3-4: sfcf values under different reset conditions (sst89e/v516rd2) . . . . . . . . . . . . . . . . . . 14 table 3-5: external data memory rd#, wr# with extram bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3-6: flashflex51 sfr memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3-7: cpu related sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3-8: flash memory programming sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3-9: watchdog timer sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3-10: timer/counters sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3-11: interface sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 3-12: pca sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4-1: external host mode commands for sst89e/v5xrd2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 4-2: external host mode commands for sst89e/v516rd2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 4-3: product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 4-4: additional read commands in external host mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 4-5: iap address resolution for sst89e/v516rd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 4-6: iap commands for sst89e/v516rd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 4-7: iap commands for sst89e/v5xrd2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 5-1: timer/counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 5-2: timer/counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 5-3: timer/counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 8-1: pca timer/counter source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 8-2: pca timer/counter inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 8-3: cmod values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 8-4: pca high and low register compare/capture modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 8-5: pca module modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 8-6: pca module modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 8-7: pulse width modulator frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 9-1: security lock options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 9-2: security lock access table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 11-1: interrupt polling sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 12-1: power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 13-1: recommended values for c1 and c2 by crystal type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 13-2: clock doubling features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 14-1: operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 14-2: reliability characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 14-3: ac conditions of test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 14-4: recommended system power-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 14-5: pin impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 14-6: dc electrical characteristics for sst89e5xxrd2: v dd = 4.5-5.5v . . . . . . . . . . . . . . . . . . . 70 table 14-7: dc electrical characteristics for sst89v5xxrd2: v dd = 2.7-3.6v . . . . . . . . . . . . . . . . . . . 72 table 14-8: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 14-9: external clock drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 14-10: serial port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 14-11: external mode flash memory programming/verification parameters . . . . . . . . . . . . . . . . 81 table 16-1: revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 7 ?2004 silicon storage technology, inc. s71255-00-000 3/04 1.0 functional blocks 10 interrupts superflash eeprom primary block 8k/16k/32k/64k x8 secondary block 8k x8 i/o i/o i/o i/o watchdog timer interrupt control 8051 cpu core ram 1k x8 security lock i/o port 0 i/o port 1 i/o port 2 i/o port 3 enhanced uart spi timer 0 (16-bit) timer 1 (16-bit) timer 2 (16-bit) 8 8 8 8 1255 b1.0 pca i/o i/o port 4 4 flash control unit 8 oscillator alu, acc, b-register, instruction register, program counter, timing and control f unctional b lock d iagram
8 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 2.0 pin assignments figure 2-1: p in a ssignments for 40- pin pdip figure 2-2: p in a ssignments for 44- lead tqfp figure 2-3: p in a ssignments for 44- lead plcc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (t2) p1.0 (t2 ex) p1.1 (eci) p1.2 (cex0) p1.3 (cex1 / ss#) p1.4 (cex2 / mosi) p1.5 (cex3 / miso) p1.6 (cex4 / sck) p1.7 rst (rxd) p3.0 (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) 40-pin pdip to p v i e w 1255 40-pdip pi p1.0 (cex2 / mosi) p1.5 (cex3 / miso) p1.6 (cex4 / sck) p1.7 rst (rxd) p3.0 int2#/p4.3 (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# p4.1 ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) p1.4 (ss# / cex1) p1.3 (cex0) p1.2 (eci) p1.1 (t2 ex) p1.0 (t2) p4.2/int3# v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss p4.0 (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 1255 44-tqfp tqj p2.0 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 44-lead tqfp top view 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 (cex2 / mosi) p1.5 (cex3 / miso) p1.6 (cex4 / sck) p1.7 rst (rxd) p3.0 int2#/p4.3 (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# p4.1 ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 p1.4 (ss# / cex1) p1.3 (cex0) p1.2 (eci) p1.1 (t2 ex) p1.0 (t2) p4.2/int3# v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss p4.0 (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 44-lead plcc top view 1255 44-plcc nj p3.0
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 9 ?2004 silicon storage technology, inc. s71255-00-000 3/04 2.1 pin descriptions table 2-1: p in d escriptions (1 of 2) symbol type 1 name and functions p0[7:0] i/o port 0: port 0 is an 8-bit open drain bi-directional i/o port. as an output port each pin can sink several ls ttl inputs. port 0 pins float that have ?1?s written to them, and in this state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external memory. in this application, it uses strong internal pull- ups when transitioning to v oh. port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during the external host mode verification. external pull-ups are required during program verification. p1[7:0] i/o with internal pull-ups port 1: port 1 is an 8-bit bi-directional i/o port with internal pull-ups. the port 1 output buff- ers can drive ls ttl inputs. port 1 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. p1[5, 6, 7] have high current drive of 16 ma. port 1 also receives the low-order address bytes during the external host mode programming and verification. p1[0] i/o t2: external count input to timer/counter 2 or clock-out from timer/counter 2 p1[1] i t2ex: timer/counter 2 capture/reload trigger and direction control p1[2] i eci: pca timer/counter external input: this signal is the external clock input for the pca timer/counter. p1[3] i/o cex0: compare/capture module external i/o each compare/capture module connects to a port 1 pin for external i/o. when not used by the pca, this pin can handle standard i/o. p1[4] i/o ss#: master input or slave output for spi. or cex1: compare/capture module external i/o p1[5] i/o mosi: master output line, slave input line for spi or cex2: compare/capture module external i/o p1[6] i/o miso: master input line, slave output line for spi or cex3: compare/capture module external i/o p1[7] i/o sck: master clock output, slave clock input line for spi or cex4: compare/capture module external i/o p2[7:0] i/o with internal pull-up port 2: port 2 is an 8-bit bi-directional i/o port with internal pull-ups. port 2 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 2 pins that are externally pulled low will source current because of the internal pull-ups. port 2 sends the high-order address byte during fetches from external pro- gram memory and during accesses to external data memory that use 16-bit address (movx@dptr). in this application, it uses strong internal pull-ups when transitioning to v oh . port 2 also receives some control signals and a partial of high-order address bits dur- ing the external host mode programming and verification. p3[7:0] i/o with internal pull-up port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. the port 3 output buff- ers can drive ls ttl inputs. port 3 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. port 3 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification. p3[0] i rxd: universal asynchronous receiver/transmitter (uart) - receive input p3[1] o txd: uart - transmit output p3[2] i int0#: external interrupt 0 input
10 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 p3[3] i int1#: external interrupt 1 input p3[4] i t0: external count input to timer/counter 0 p3[5] i t1: external count input to timer/counter 1 p3[6] o wr#: external data memory write strobe p3[7] o rd#: external data memory read strobe psen# i/o program store enable: psen# is the read strobe to external program store. when the device is executing from internal program memory, psen# is inactive (v oh ). when the device is executing code from external program memory, psen# is activated twice each machine cycle, except when access to external data memory while one psen# activation is skipped in each machine cycle. a forced high-to-low input transition on the psen# pin while the rst input is continually held high for more than ten machine cycles will cause the device to enter external host mode for programming. rst i reset: while the oscillator is running, a high logic state on this pin for two machine cycles will reset the device. after a reset, if the psen# pin is driven by a high-to-low input transition while the rst input pin is held high, the device will enter the external host mode, otherwise the device will enter the normal operation mode. ea# i external access enable: ea# must be driven to v il in order to enable the device to fetch code from the external program memory. ea# must be driven to v ih for internal program execution. however, security lock level 4 will disable ea#, and program execution is only possible from internal program memory. the ea# pin can tolerate a high voltage 2 of 12v. ale/prog# i/o address latch enable: ale is the output signal for latching the low byte of the address during an access to external memory. this pin is also the programming pulse input (prog#) for flash programming. normally the ale 3 is emitted at a constant rate of 1/6 the crystal frequency 4 and can be used for external timing and clocking. one ale pulse is skipped during each access to external data memory. however, if ao is set to 1, ale is dis- abled. p4[3:0] 5 i/o with internal pull-ups port 4: port 4 is an 4-bit bi-directional i/o port with internal pull-ups. the port 4 output buff- ers can drive ls ttl inputs. port 4 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 4 pins that are exter- nally pulled low will source current because of the internal pull-ups. p4[0] i/o bit 0 of port 4 p4[1] i/o bit 1 of port 4 p4[2] / int3# i/o bit 2 of port 4 / int3# external interrupt 3 input p4[3] / int2# i/o bit 3 of port 4 / int2# external interrupt 2 input xtal1 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 o crystal 2: output from the inverting oscillator amplifier v dd i power supply v ss i ground t2-1.0 1255 1. i = input; o = output 2. it is not necessary to receive a 12v programming supply voltage during flash programming. 3. ale loading issue: when ale pin experiences higher loading (>30pf ) during the reset, the mcu may accidentally enter into mode s other than normal working mode. the solution is to add a pull-up resistor of 3-50 k ? to v dd , e.g. for ale pin. 4. for 6 clock mode, ale is emitted at 1/3 of crystal frequency. 5. port 4 is not present on the pdip package. table 2-1: p in d escriptions (c ontinued ) (2 of 2) symbol type 1 name and functions
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 11 ?2004 silicon storage technology, inc. s71255-00-000 3/04 3.0 memory organization the device has separate address spaces for program and data memory. 3.1 program flash memory there are two internal flash memory blocks in the device. the primary flash memory block (block 0) has 8/16/32/64 kbyte. the secondary flash memory block (block 1) has 8 kbyte. since the total program address space is limited to 64 kbyte, the sfcf[1:0] bit are used to control program bank selection. please refer to figures 3-1 through 3-4 for the program memory configuration. program bank selec- tion is described in the next section. the 8k/16k/32k/64k x8 primary superflash block is orga- nized as 64/128/256/512 sectors, each sector consists of 128 bytes. the 8k x8 secondary superflash block is organized as 64 sectors, each sector consists also of 128 bytes. for both blocks, the 7 least significant program address bits select the byte within the sector. the remainder of the pro- gram address bits select the sector within the block. figure 3-1: p rogram m emory o rganization for 8 kb yte sst89e/v52rd2 1255 f01.0 external 64 kbyte ea# = 0 ffffh 0000h 8 kbyte block 0 ea# = 1 sfcf[1:0] = 10, 11 ffffh 0000h 8 kbyte block 1 8 kbyte block 1 ea# = 1 sfcf[1:0] = 00 ffffh 2000h dfffh e000h dfffh e000h 7fffh 8000h 0000h 1fffh not accessible not accessible not accessible 8 kbyte block 1 ea# = 1 sfcf[1:0] = 01 ffffh 7fffh 8000h 0000h 8 kbyte block 0
12 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 3-2: p rogram m emory o rganization for 16 kb yte sst89e/v54rd2 figure 3-3: p rogram m emory o rganization for 32 kb yte sst89e/v58rd2 1255 f02.0 external 64 kbyte ea# = 0 ffffh 0000h 16 kbyte block 0 ea# = 1 sfcf[1:0] = 10, 11 ffffh 0000h 8 kbyte block 0 8 kbyte block 1 8 kbyte block 1 ea# = 1 sfcf[1:0] = 00 ffffh 2000h 7fffh 8000h dfffh e000h dfffh e000h 7fffh 8000h 0000h 1fffh not accessible not accessible not accessible 8 kbyte block 1 ea# = 1 sfcf[1:0] = 01 ffffh 7fffh 8000h 0000h 16 kbyte block 0 1255 f03.0 external 64 kbyte ea# = 0 ffffh 0000h 32 kbyte block 0 ea# = 1 sfcf[1:0] = 10, 11 ffffh 0000h 24 kbyte block 0 8 kbyte block 1 8 kbyte block 1 ea# = 1 sfcf[1:0] = 00 ffffh 2000h 7fffh 8000h dfffh e000h dfffh e000h 7fffh 8000h 0000h 1fffh external 24 kbyte 8 kbyte block 1 external 24 kbyte external 32 kbyte ea# = 1 sfcf[1:0] = 01 ffffh 7fffh 8000h 0000h 32 kbyte block 0
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 13 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 3-4: p rogram m emory o rganization for 64 kb yte sst89e/v516rd2 3.2 program memory block switching the program memory block switching feature of the device allows either block 1 or the lowest 8 kbyte of block 0 to be used for the lowest 8 kbyte of the program address space. sfcf[1:0] controls program memory block switching. 1255 f04.0 external 64 kbyte ea# = 0 ffffh 0000h 64 kbyte block 0 ea# = 1 sfcf[1:0] = 01, 10, 11 ffffh 0000h 56 kbyte block 0 8 kbyte block 1 ea# = 1 sfcf[1:0] = 00 ffffh 2000h 0000h 1fffh table 3-1: sfcf v alues for p rogram m emory b lock s witching for sst89e/v516rd2 sfcf[1:0] program memory block switching 01, 10, 11 block 1 is not visible to the program counter (pc). block 1 is reachable only via in-application programming from 0000h - 1fffh. 00 block 1 is overlaid onto the low 8k of the program address space; occupying address locations 0000h - 1fffh. when the pc falls within 0000h - 1fffh, the instruction will be fetched from block 1 instead of block 0. outside of 0000h - 1fffh, block 0 is used. locations 0000h - 1fffh of block 0 are reachable through in-application programming. t3-1.0 1255 table 3-2: sfcf v alues for p rogram m emory b lock s witching for sst89e/v5 x rd2 sfcf[1:0] program memory block switching 10, 11 block 1 is not visible to the pc; block 1 is reachable only via in-application programming from e000h - ffffh. 01 both block 0 and block 1 are visible to the pc. block 0 is occupied from 0000h - 7fffh. block 1 is occupied from e000h - ffffh. 00 block 1 is overlaid onto the low 8k of the program address space; occupying address locations 0000h - 1fffh. when the pc falls within 0000h - 1fffh, the instruction will be fetched from block 1 instead of block 0. outside of 0000h - 1fffh, block 0 is used. locations 0000h - 1fffh of block 0 are reachable through in-application programming. t3-2.0 1255
14 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 3.2.1 reset configuration of program memory block switching program memory block switching is initialized after reset according to the state of the start-up configuration bit sc0 and/or sc1. the sc0 and sc1 bits are programmed via an external host mode command or an iap mode com- mand. see table 4-1, table 4-6, and table 4-7. once out of reset, the sfcf[0] bit can be changed dynam- ically by the program for desired effects. changing sfcf[0] will not change the sc0 bit. caution must be taken when dynamically changing the sfcf[0] bit. since this will cause different physical memory to be mapped to the logical program address space. the user must avoid executing block switching instructions within the address range 0000h to 1fffh. 3.3 data ram memory the data ram has 1024 bytes of internal memory. the ram can be addressed up to 64kb for external data memory. 3.4 expanded data ram addressing the sst89e/v554a both have the capability of 1k of ram. see figure 3-5. the device has four sections of internal data memory: 1. the lower 128 bytes of ram (00h to 7fh) are directly and indirectly addressable. 2. the higher 128 bytes of ram (80h to ffh) are indirectly addressable. 3. the special function registers (80h to ffh) are directly addressable only. 4. the expanded ram of 768 bytes (00h to 2ffh) is indirectly addressable by the move external instruction (movx) and clearing the extram bit. (see ?auxiliary register (auxr)? in section 3.6, ?special function registers?) since the upper 128 bytes occupy the same addresses as the sfrs, the ram must be accessed indirectly. the ram and sfrs space are physically separate even though they have the same addresses. when instructions access addresses in the upper 128 bytes (above 7fh), the mcu determines whether to access the sfrs or ram by the type of instruction given. if it is indirect, then ram is accessed. if it is direct, then an sfr is accessed. see the examples below. indirect access: mov @r0, #data ; r0 contains 90h register r0 points to 90h which is located in the upper address range. data in ?#data? is written to ram location 90h rather than port 1. direct access: mov 90h, #data ; write data to p1 data in ?#data? is written to port 1. instructions that write directly to the address write to the sfrs. to access the expanded ram, the extram bit must be cleared and movx instructions must be used. the extra 768 bytes of memory is physically located on the chip and logically occupies the first 768 bytes of external memory (addresses 000h to 2ffh). when extram = 0, the expanded ram is indirectly addressed using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. accessing the expanded ram does not affect ports p0, p3.6 (wr#), p3.7 (rd#), or p2. with extram = 0, the expanded ram can be accessed as in the following example. table 3-3: sfcf v alues u nder d ifferent r eset c onditions (sst89e/v5 x rd2) sc1 1 1. p = programmed (bit logic state = 0), u = unprogrammed (bit logic state = 1) sc0 1 state of sfcf[1:0] after: power-on or external reset wdt reset or brown-out reset software reset u (1) u (1) 00 (default) x0 10 u (1) p (0) 01 x1 11 p (0) u (1) 10 10 10 p (0) p (0) 11 11 11 t3-3.0 1255 table 3-4: sfcf v alues u nder d ifferent r eset c onditions (sst89e/v516rd2) sc0 1 1. p = programmed (bit logic state = 0), u = unprogrammed (bit logic state = 1) state of sfcf[1:0] after: power-on or external reset wdt reset or brown-out reset software reset u (1) 00 (default) x0 10 p (0) 01 x1 11 t3-4.0 1255
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 15 ?2004 silicon storage technology, inc. s71255-00-000 3/04 expanded ram access (indirect addressing only): movx @dptr, a ; dptr contains 0a0h dptr points to 0a0h and data in ?a? is written to address 0a0h of the expanded ram rather than external memory. access to external memory higher than 2ffh using the movx instruction will access external memory (0300h to ffffh) and will perform in the same way as the standard 8051, with p0 and p2 as data/address bus, and p3.6 and p3.7 as write and read timing signals. when extram = 1, movx @ri and movx @dptr will be similar to the standard 8051. using movx @ri pro- vides an 8-bit address with multiplexed data on port 0. other output port pins can be used to output higher order address bits. this provides external paging capabilities. using movx @dptr generates a 16-bit address. this allows external addressing up the 64k. port 2 provides the high-order eight address bits (dph), and port 0 multiplexes the low order eight address bits (dpl) with data. both movx @ri and movx @dptr generates the necessary read and write signals (p3.6 - wr# and p3.7 - rd#) for external memory use. table 3-5 shows external data mem- ory rd#, wr# operation with extram bit. the stack pointer (sp) can be located anywhere within the 256 bytes of internal ram (lower 128 bytes and upper 128 bytes). the stack pointer may not be located in any part of the expanded ram. table 3-5: e xternal d ata m emory rd#, wr# with extram bit movx @dptr, a or movx a, @dptr movx @ri, a or movx a, @ri auxr addr < 0300h addr >= 0300h addr = any extram = 0 rd# / wr# not asserted rd# / wr# asserted rd# / wr# not asserted 1 1. access limited to eram address within 0 to 0ffh; cannot access 100h to 02ffh. extram = 1 rd# / wr# asserted rd# / wr# asserted rd# / wr# asserted t3-5.0 1255
16 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 3-5: i nternal and e xternal d ata m emory s tructure 000h 2ffh 00h ffh upper 128 bytes internal ram lower 128 bytes internal ram (indirect & direct addressing) (indirect addressing) (direct addressing) special function registers (sfrs) 80h ffh ffffh 000h external data memory 2ffh 0000h external data memory extram = 0 extram = 1 expanded ram 0300h (indirect addressing) ffffh (indirect addressing) (indirect addressing) 80h 7fh 1255 f05.0 expanded ram 768 bytes
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 17 ?2004 silicon storage technology, inc. s71255-00-000 3/04 3.5 dual data pointers the device has two 16-bit data pointers. the dptr select (dps) bit in auxr1 determines which of the two data pointers is accessed. when dps=0, dptr0 is selected; when dps=1, dptr1 is selected. quickly switching between the two data pointers can be accomplished by a single inc instruction on auxr1. (see figure 3-6) figure 3-6: d ual d ata p ointer o rganization 3.6 special function registers most of the unique features of the flashflex51 microcontroller family are controlled by bits in special function regis- ters (sfrs) located in the sfr memory map shown in table 3-6. individual descriptions of each sfr are provided and reset values indicated in tables 3-7 to 3-11. table 3-6: f lash f lex 51 sfr m emory m ap 8 bytes f8h ip1 1 1. bit addressable sfrs ch ccap0h ccap1h ccap2h ccap3h ccap4h ffh f0h b 1 ip1h f7h e8h iea 1 cl ccap0l ccap1l ccap2 l ccap3l ccap4l efh e0h acc 1 e7h d8h ccon 1 cmod ccapm0 ccapm1 ccapm2 ccapm3 ccapm4 dfh d0h psw 1 spcr d7h c8h t2con 1 t2mod rcap2l rcap2h tl2 th2 cfh c0h wdtc 1 c7h b8h ip 1 saden bfh b0h p3 1 sfcf sfcm sfal sfah sfdt sfst iph b7h a8h ie 1 saddr spsr xicon afh a0h p2 1 auxr1 p4 a7h 98h scon 1 sbuf 9fh 90h p1 1 97h 88h tcon 1 tmod tl0 tl1 th0 th1 auxr 8fh 80h p0 1 sp dpl dph wdtd spdr pcon 87h t3-6.0 1255 dpl 82h dps = 0 dptr0 dps = 1 dptr1 external data memory dps 1255 f06.0 dph 83h dptr0 dptr1 auxr1 / bit0
18 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 3-7: cpu related sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb acc 1 accumulator e0h acc[7:0] 00h b 1 b register f0h b[7:0] 00h psw 1 program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h sp stack pointer 81h sp[7:0] 07h dpl data pointer low 82h dpl[7:0] 00h dph data pointer high 83h dph[7:0] 00h ie 1 interrupt enable a8h ea ec et2 es et1 ex1 et0 ex0 00h iea 1 interrupt enable a e8h - - - - ebo - - - xxxx0xxxb ip 1 interrupt priority reg b8h - ppc pt2 ps pt1 px1 pt0 px0 x0000000b iph interrupt priority reg high b7h - ppch pt2h psh pt1h px1h pt0h px0h x0000000b ip1 1 interrupt priority reg a f8h - - - - pbo - - - xxxx0xxxb ip1h interrupt priority reg a high f7h - - - - pboh - - - xxxx0xxxb pcon power control 87h smod1 smod0 bof pof gf1 gf0 pd idl 00010000b auxr auxiliary reg 8eh - - - - - - extram ao xxxxxxx00b auxr1 auxiliary reg 1 a2h - - - - gf2 0 - dps xxxx00x0b xicon external interrupt control aeh 0 ex3 ie3 it3 0 ex2 ie2 it2 00h t3-7.0 1255 1. bit addressable sfrs table 3-8: f lash m emory p rogramming sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sfcf superflash configuration b1h - iapen - - - - swr bsel x0xxxx00b sfcm superflash command b2h fie fcm[6:0] 00h sfal superflash address low b3h superflash low order byte address register - a 7 to a 0 (sfal) 00h sfah superflash address high b4h superflash high order byte address register - a 15 to a 8 (sfah) 00h sfdt superflash data b5h superflash data register 00h sfst superflash status b6h sb1_i sb2_i sb3_i - edc_i flash_busy - - 000x00xxb t3-8.0 1255
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 19 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 3-9: w atchdog t imer sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb wdtc 1 watchdog timer control c0h - - - wdout wdre wdts wdt swdt xxx00x00b wdtd watchdog timer data/reload 85h watchdog timer data/reload 00h t3-9.0 1255 1. bit addressable sfrs table 3-10: t imer /c ounters sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb tmod timer/counter mode control 89h timer 1 timer 0 00h gate c/t# m1 m0 gate c/t# m1 m0 tcon 1 1. bit addressable sfrs timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer 0 msb 8ch th0[7:0] 00h tl0 timer 0 lsb 8ah tl0[7:0] 00h th1 timer 1 msb 8dh th1[7:0] 00h tl1 timer 1 lsb 8bh tl1[7:0] 00h t2con 1 timer / counter 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# 00h t2mod# timer2 mode control c9h---- - -t2oedcenxxxxxx00b th2 timer 2 msb cdh th2[7:0] 00h tl2 timer 2 lsb cch tl2[7:0] 00h rcap2h timer 2 capture msb cbh rcap2h[7:0] 00h rcap2l timer 2 capture lsb cah rcap2l[7:0] 00h t3-10.0 1255
20 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 3-11: i nterface sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sbuf serial data buffer 99h sbuf[7:0] indeterminate scon 1 serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h saddr slave address a9h saddr[7:0] 00h saden slave address mask b9h saden[7:0] 00h spcr spi control register d5h spie spe dord mstr cpol cpha spr1 spr0 04h spsr spi status register aah spif wcol 00h spdr spi data register 86h spdr[7:0] 00h p0 1 port 0 80h p0[7:0] ffh p1 1 port 1 90h - - - - - - t2ex t2 ffh p2 1 port 2 a0h p2[7:0] ffh p3 1 port 3 b0h rd# wr# t1 t0 int1# int0# txd rxd ffh p4 2 port 4 a5h 1 1 1 1 p4.3 p4.2 p4.1 p4.0 ffh t3-11.0 1255 1. bit addressable sfrs 2. p4 is similar to p1 and p3 ports
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 21 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 3-12: pca sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb ch cl pca timer/counter f9h e9h ch[7:0] cl[7:0] 00h 00h ccon 1 pca timer/counter control register d8h cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 00x00000b cmod pca timer/counter mode register d9h cidl wdte - - - cps1 cps0 ecf 00xxx000b ccap0h pca module 0 compare/capture registers fah ccap0h[7:0] 00h ccap0l eah ccap0l[7:0] 00h ccap1h pca module 1 compare/capture registers fbh ccap1h[7:0] 00h ccap1l ebh ccap1l[7:0] 00h ccap2h pca module 2 compare/capture registers fch ccap2h[7:0] 00h ccap2l ech ccap2l[7:0] 00h ccap3h pca module 3 compare/capture registers fdh ccap3h[7:0] 00h ccap3l edh ccap3l[7:0] 00h ccap4h pca module 4 compare/capture registers feh ccap4h[7:0] 00h ccap4l eeh ccap4l[7:0] 00h ccapm0 pca compare/capture module mode registers dah - ecom0 capp0 capn0 mat0 tog0 pwm0 eccf0 x0000000b ccapm1 dbh - ecom1 capp1 capn1 mat1 tog1 pwm1 eccf1 x0000000b ccapm2 dch - ecom2 capp2 capn2 mat2 tog2 pwm2 eccf2 x0000000b ccapm3 ddh - ecom3 capp3 capn3 mat3 tog3 pwm3 eccf3 x0000000b ccapm4 deh - ecom4 capp4 capn4 mat4 tog4 pwm4 eccf4 x0000000b t3-12.0 1255 1. bit addressable sfrs
22 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function iapen enable iap operation 0: iap commands are disabled 1: iap commands are enabled swr software reset see section 10.2, ?software reset? bsel program memory block switching bit see figures 3-1 through 3-4 and tables 3-3 and 3-4 symbol function fie flash interrupt enable. 0: int1# is not reassigned. 1: int1# is re-assigned to signal iap operation completion. external int1# interrupts are ignored. fcm[6:0] flash operation command 000_0001b chip-erase 000_1011b sector-erase 000_1101b block-erase 000_1100b byte-verify 1 000_1110b byte-program 000_1111b prog-sb1 000_0011b prog-sb2 000_0101b prog-sb3 000_1001b prog-sc0 000_1001b prog-sc1 000_1000benable-clock-double all other combinations are not implemented, and reserved for future use. 1. byte-verify has a single machine cycle latency and will not generate any int1# interrupt regardless of fie. symbol function sfal mailbox register for interfacing with flash memory block. (low order address register). symbol function sfah mailbox register for interfacing with flash memory block. (high order address register). superflash configuration register (sfcf) location76543210reset value b1h - iapen ----swr bsel x0xxxx00b superflash command register (sfcm) location76543210reset value b2h fie fcm6 fcm5 fcm4 fcm3 fcm2 fc m1 fcm0 00h superflash address registers (sfal) location76543210reset value b3h superflash low order byte address register 00h superflash address registers (sfah) location76543210reset value b4h superflash high order byte address register 00h
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 23 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function sfdt mailbox register for interfacing with flash memory block. (data register). symbol function sb1 _i security bit 1 status (inverse of sb1 bit) sb2 _i security bit 2 status (inverse of sb2 bit) sb3 _i security bit 3 status (inverse of sb3 bit) please refer to table 9-1 for security lock options. edc _i double clock status 0: 12 clocks per machine cycle 1: 6 clocks per machine cycle flash_busy flash operation completion polling bit. 0: device has fully completed the last iap command. 1: device is busy with flash operation. superflash data register (sfdt) location76543210reset value b5h superflash data register 00h superflash status register (sfst) (read only register) location76543 2 10reset value b6h sb1_i sb2_i sb3_i - edc_i flash_busy - - xxxxx0xxb
24 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function ea global interrupt enable. 0 = disable 1 = enable ec pca interrupt enable. et2 timer 2 interrupt enable. es serial interrupt enable. et1 timer 1 interrupt enable. ex1 external 1 interrupt enable. et0 timer 0 interrupt enable. ex0 external 0 interrupt enable. symbol function ebo brown-out interrupt enable. 1 = enable the interrupt 0 = disable the interrupt interrupt enable (ie) location76543210reset value a8h ea ec et2 es et1 ex1 et0 ex0 00h interrupt enable a (iea) location76543210reset value e8h----ebo---xxxx0xxxb
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 25 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function ppc pca interrupt priority bit pt2 timer 2 interrupt priority bit ps serial port interrupt priority bit pt1 timer 1 interrupt priority bit px1 external interrupt 1 priority bit pt0 timer 0 interrupt priority bit px0 external interrupt 0 priority bit symbol function ppch pca interrupt priority bit high pt2h timer 2 interrupt priority bit high psh serial port interrupt priority bit high pt1h timer 1 interrupt priority bit high px1h external interrupt 1 priority bit high pt0h timer 0 interrupt priority bit high px0h external interrupt 0 priority bit high symbol function pbo brown-out interrupt priority bit px2 external interrupt 2 priority bit px3 external interrupt 3 priority bit symbol function pboh brown-out interrupt priority bit high px2h external interrupt 2 priority bit high px3h external interrupt 3 priority bit high interrupt priority (ip) location76543210reset value b8h - ppc pt2 ps pt1 px1 pt0 px0 x0000000b interrupt priority high (iph) location76543210reset value b7h - ppch pt2h psh pt1h px1h pt0h px0h x0000000b interrupt priority 1 (ip1) location76543210reset value f8h 1 - - 1 pbo px3 px2 1 1xx10001b interrupt priority 1 high (ip1h) location76543210reset value f7h 1 - - 1 pboh px3h px2h 1 1xx10001b
26 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function extram internal/external ram access 0: internal expanded ram access within range of 00h to 2ffh using movx @ri / @dptr. beyond 300h, the mcu always accesses external data memory. for details, refer to section 3.4, ?expanded data ram addressing? . 1: external data memory access. ao disable/enable ale 0: ale is emitted at a constant rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 f osc in 12 clock mode. 1: ale is active only during a movx or movc instruction. symbol function gf2 general purpose user-defined flag. dps dptr registers select bit. 0: dptr0 is selected. 1: dptr1 is selected. symbol function wdout watchdog output enable. 0: watchdog reset will not be exported on reset pin. 1: watchdog reset if enabled by wdre, will assert reset pin for 32 clocks. wdre watchdog timer reset enable. 0: disable watchdog timer reset. 1: enable watchdog timer reset. wdts watchdog timer reset flag. 0: external hardware reset or power-on reset clears the flag. flag can also be cleared by writing a 1. flag survives if chip reset happened because of watchdog timer overflow. 1: hardware sets the flag on watchdog overflow. wdt watchdog timer refresh. 0: hardware resets the bit when refresh is done. 1: software sets the bit to force a watchdog timer refresh. swdt start watchdog timer. 0: stop wdt. 1: start wdt. auxiliary register (auxr) location76543210reset value 8eh------extramaoxxxxxx00b auxiliary register 1 (auxr1) location76543210reset value a2h----gf20-dpsxxxx00x0b watchdog timer control register (wdtc) location76543210reset value c0h - - - wdout wdre wdts wdt swdt xxx00000b
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 27 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function wdtd initial/reload value in watchdog timer. new value won?t be effective until wdt is set. symbol function cf pca counter overflow flag set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software, but can only cleared by software. cr pca counter run control bit set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. - not implemented, reserved for future use. note: user should not write ?1?s to reserved bits. the value read from a reserved bit is indeterminate. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. watchdog timer data/reload register (wdtd) location76543210reset value 85h watchdog timer data/reload 00h pca timer/counter control register 1 (ccon) 1. bit addressable location76543210reset value d8h cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 00x00000b
28 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function cidl counter idle control: 0: programs the pca counter to continue functioning during idle mode 1: programs the pca counter to be gated off during idle wdte watchdog timer enable: 0: disables watchdog timer function on pca module 4 1: enables watchdog timer function on pca module 4 - not implemented, reserved for future use. note: user should not write ?1?s to reserved bits. the value read from a reserved bit is indeterminate. cps1 pca count pulse select bit 1 cps0 pca count pulse select bit 2 ecf pca enable counter overflow interrupt: 0: disables the cf bit in ccon 1: enables cf bit in ccon to generate an interrupt pca timer/counter mode register 1 (cmod) location76543210reset value d9h cidl wdte - - - cps1 cps0 ecf 00xxx000b 1. not bit addressable cps1 cps0 selected pca input 1 1. f osc = oscillator frequency 00 0 internal clock, f osc /6 in 6 clock mode (f osc /12 in 12 clock mode) 01 1 internal clock, f osc /2 in 6 clock mode (f osc /4 in 12 clock mode) 10 2 timer 0 overflow 11 3 external clock at eci/p1.2 pin (max. rate = f osc /4 in 6 clock mode, f osc /8 in 12 clock mode)
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 29 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function - not implemented, reserved for future use. note: user should not write ?1?s to reserved bits. the value read from a reserved bit is indeterminate. ecomn enable comparator 0: disables the comparator function 1: enables the comparator function cappn capture positive 0: disables positive edge capture on cex[4:0] 1: enables positive edge capture on cex[4:0] capnn capture negative 0: disables negative edge capture on cex[4:0] 1: enables negative edge capture on cex[4:0] matn match: set ecom[4:0] and mat[4:0] to implement the software timer mode 0: disables software timer mode 1: a match of the pca counter with this module?s compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle 0: disables toggle function 1: a match of the pca counter with this module?s compare/capture register causes the the cexn pin to toggle. pwmn pulse width modulation mode 0: disables pwm mode 1: enables cexn pin to be used as a pulse width modulated output eccfn enable ccf interrupt 0: disables compare/capture flag ccf[4:0] in the ccon register to generate an interrupt request. 1: enables compare/capture flag ccf[4:0] in the ccon register to generate an interrupt request. pca compare/capture module mode register 1 (ccapmn) location76543210reset value dah - ecom0 capp0 capn0 mat0 tog0 pwm0 eccf0 00xxx000b dbh - ecom1 capp1 capn1 mat1 tog1 pwm1 eccf1 00xxx000b dch - ecom2 capp2 capn2 mat2 tog2 pwm2 eccf2 00xxx000b ddh - ecom3 capp3 capn3 mat3 tog3 pwm3 eccf3 00xxx000b deh - ecom4 capp4 capn4 mat4 tog4 pwm4 eccf4 00xxx000b 1. not bit addressable
30 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function spie if both spie and es are set to one, spi interrupts are enabled. spe spi enable bit. 0: disables spi. 1: enables spi and connects ss#, mosi, miso, and sck to pins p1.4, p1.5, p1.6, p1.7. dord data transmission order. 0: msb first in data transmission. 1: lsb first in data transmission. mstr master/slave select. 0: selects slave mode. 1: selects master mode. cpol clock polarity 0: sck is low when idle (active high). 1: sck is high when idle (active low). cpha clock phase control bit. 0: shift triggered on the leading edge of the clock. 1: shift triggered on the trailing edge of the clock. spr1, spr0 spi clock rate select bits. these two bits control the sck rate of the device configured as master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator frequency, f osc , is as follows: symbol function spif spi interrupt flag. upon completion of data transfer, this bit is set to 1. if spie =1 and es =1, an interrupt is then generated. this bit is cleared by software. wcol write collision flag. set if the spi data register is written to during data transfer. this bit is cleared by software. spi control register (spcr) location76543210reset value d5h spie spe dord mstr cpol cpha spr1 spr0 00h spr1 spr0 sck = f osc divided by 0 0 1 1 0 1 0 1 4 16 64 128 spi status register (spsr) location76543210reset value aahspifwcol------00xxxxxxb
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 31 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function smod1 double baud rate bit. if smod1 = 1, timer 1 is used to generate the baud rate, and the serial port is used in modes 1, 2, and 3. smod0 fe/sm0 selection bit. 0: scon[7] = sm0 1: scon[7] = fe, bof brown-out detection status bit, this bit will not be affected by any other reset. bof should be cleared by software. power-on reset will also clear the bof bit. 0: no brown-out. 1: brown-out occurred pof power-on reset status bit, this bit will not be affected by any other reset. pof should be cleared by software. 0: no power-on reset. 1: power-on reset occurred gf1 general-purpose flag bit. gf0 general-purpose flag bit. pd power-down bit, this bit is cleared by hardware after exiting from power-down mode. 0: power-down mode is not activated. 1: activates power-down mode. idl idle mode bit, this bit is cleared by hardware after exiting from idle mode. 0: idle mode is not activated. 1: activates idle mode. spi data register (spdr) location76543210reset value 86h spdr[7:0] 00h power control register (pcon) location76543210reset value 87h smod1 smod0 bof pof gf1 gf0 pd idl 00010000b
32 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function fe set smod0 = 1 to access fe bit. 0: no framing error 1: framing error. set by receiver when an invalid stop bit is detected. this bit needs to be cleared by software. sm0 smod0 = 0 to access sm0 bit. serial port mode bit 0 sm1 serial port mode bit 1 sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then ri will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then ri will not be activated unless a valid stop bit was received. in mode 0, sm2 should be 0. ren enables serial reception. 0: to disable reception. 1: to enable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission, must be cleared by software. ri receive interrupt flag. set by hardware at the end of the8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. serial port control register (scon) location76543210reset value 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00000000b sm0 sm1 mode description baud rate 1 1. f osc = oscillator frequency 0 0 0 shift register f osc /6 (6 clock mode) or f osc /12 (12 clock mode) 0 1 1 8-bit uart variable 1029-bit uartf osc /32 or f osc /16 (6 clock mode) or f osc /64 or f osc /32 (12 clock mode) 1 1 3 9-bit uart variable
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 33 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function tf2 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1. exf2 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk receive clock flag. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflow to be used for the transmit clock. exen2 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 start/stop control for timer 2. a logic 1 starts the timer. c/t2# timer or counter select (timer 2) 0: internal timer (osc/6 in 6 clock mode, osc/12 in 12 clock mode) 1: external event counter (falling edge triggered) cp/rl2# capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. symbol function - not implemented, reserved for future use. note: user should not write ?1?s to reserved bits. the value read from a reserved bit is indeterminate. t2oe timer 2 output enable bit. dcen down count enable bit. when set, this allows timer 2 to be configured as an up/down counter. timer/counter 2 control register (t2con) location76543210reset value c8h tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# 00h timer/counter 2 mode control (t2mod) location76543210reset value c9h------t2oedcenxxxxxx00b
34 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 symbol function ex2 external interrupt 2 enable bit if set ie2 interrupt enable if it2=1, ie2 is set/cleared automatically by hardware when interrupt is detected/ serviced. it2 external interrupt 2 is falling-edge/low-level triggered when this bit is cleared by software. ex3 external interrupt 3 enable bit if set ie3 interrupt enable if it3=1, ie3 is set/cleared automatically by hardware when interrupt is detected/ serviced. it3 external interrupt3 is falling-edge/low-level triggered when this bit is cleared by software. external interrupt control (xicon) location76543210reset value aeh 0 ex3 ie3 it3 0 ex2 ie2 it2 00h
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 35 ?2004 silicon storage technology, inc. s71255-00-000 3/04 4.0 flash memory programming the device internal flash memory can be programmed or erased using the following two methods: external host programming mode in-application programming (iap) mode 4.1 external host programming mode external host programming mode allows the user to pro- gram the flash memory directly without using the cpu. external host mode is entered by forcing psen# from a logic high to a logic low while rst input is being held con- tinuously high. the device will stay in external host mode as long as rst = 1 and psen# = 0. a read-id operation is necessary to ?arm? the device in external host mode, and no other external host mode com- mands can be enabled until a read-id is performed. in external host mode, the internal flash memory blocks are accessed through the re-assigned i/o port pins (see figure 4-1 for details) by an external host, such as a mcu program- mer, a pcb tester or a pc-controlled development board. note: v il = input low voltage; v ih = input high voltage; v ih1 = input high voltage (xtal, rst); x = don?t care; al = address low order byte; ah = address high order byte; di = data input; do = data output; a[15:13] = 0xxb for block 0 and a[15:13] = 111b for block 1 table 4-1: e xternal h ost m ode c ommands for sst89e/v5 x rd2 operation rst psen# prog#/ ale ea# p3[7] p3[6] p2[7] p2[6] p0[7:0] p3[5:4] p2[5:0] p1[7:0] read-id v ih1 v il v ih v ih v il v il v il v il do ah al chip-erase v ih1 v il ? 1 1. symbol ? signifies a negative pulse and the command is asserted during the low state of prog#/ale input. all other combinations of the above input pins are invalid and may result in unexpected behaviors. v ih v il v il v il v ih xxx block-erase v ih1 v il ? v ih v ih v ih v il v ih x a[15:13] x sector-erase v ih1 v il ? v ih v ih v il v ih v ih xahal byte-program v ih1 v il ? v ih v ih v ih v ih v il di ah al byte-verify (read) v ih1 v il v ih v ih v ih v ih v il v il do ah al prog-sc0 v ih1 v il ? v ih v ih v il v il v ih x5ahx prog-sc1 v ih1 v il ? v ih v ih v il v il v ih x aah x prog-sb1 v ih1 v il ? v ih v ih v ih v ih v ih xxx prog-sb2 v ih1 v il ? v ih v il v il v ih v ih xxx prog-sb3 v ih1 v il ? v ih v il v ih v il v ih xxx enable-clock-double v ih1 v il ? v ih v ih v il v il v il x 55h x t4-1.0 1255
36 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 note: v il = input low voltage; v ih = input high voltage; v ih1 = input high voltage (xtal, rst); x = don?t care; al = address low order byte; ah = address high order byte; di = data input; do = data output figure 4-1: i/o p in a ssignments for e xternal h ost m ode table 4-2: e xternal h ost m ode c ommands for sst89e/v516rd2 operation rst psen# prog#/ ale ea# p3[7] p3[6] p2[7] p2[6] p0[7:0] p3[5:4] p2[5:0] p1[7:0] read-id v ih1 v il v ih v ih v il v il v il v il do ah al chip-erase v ih1 v il ? 1 v ih v il v il v il v ih xxx block-erase v ih1 v il ? v ih v ih v ih v il v ih xxx sector-erase v ih1 v il ? v ih v ih v il v ih v ih xahal byte-program v ih1 v il ? v ih v ih v ih v ih v il di ah al byte-verify (read) v ih1 v il v ih v ih v ih v ih v il v il do ah al select-block0 v ih1 v il ? v ih v ih v il v il v ih x 55h x select-block1 v ih1 v il ? v ih v ih v il v il v ih xa5hx prog-sc0 v ih1 v il ? v ih v ih v il v il v ih x5ahx prog-sb1 v ih1 v il ? v ih v ih v ih v ih v ih xxx prog-sb2 v ih1 v il ? v ih v il v il v ih v ih xxx prog-sb3 v ih1 v il ? v ih v il v ih v il v ih xxx enable-clock-double v ih1 v il ? v ih v ih v il v il v il x 55h x t4-2.0 1255 1. symbol ? signifies a negative pulse and the command is asserted during the low state of prog#/ale input. all other combinations of the above input pins are invalid and may result in unexpected behaviors. flash control signals address bus a 7 -a 0 flash control signals address bus a 13 -a 8 input/ output data bus port 0 v ss ready/busy# port 3 v dd rst port 2 port 1 ea# ale / prog# psen# 7 6 5 a 15 a 14 4 3 2 1 0 7 6 7 6 5 4 3 2 1 0 0 7 6 0 address bus a 15 -a 14 1255 f07.0
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 37 ?2004 silicon storage technology, inc. s71255-00-000 3/04 4.1.1 product identification the read-id command accesses the signature bytes that identify the device and the manufacturer as sst. external programmers primarily use these signature bytes in the selection of programming algorithms. the read-id com- mand is selected by the command code of 0h on p3[7:6] and p2[7:6]. see figure 14-14 for timing waveforms. 4.1.2 arming command an arming command sequence must take place before any external host mode sequence command is recognized by the device. this prevents accidental triggering of exter- nal host mode commands due to noise or programmer error. the arming command is as follows: 1. psen# goes low while rst is high. this will get the machine in external host mode, re-configuring the pins, and turning on the on-chip oscillator. 2. a read-id command is issued, and after 1 ms the external host mode commands can be issued. after the above sequence, all other external host mode commands are enabled. before the read-id command is received, all other external host mode commands received are ignored. 4.1.3 external host mode commands the external host mode commands are read-id, chip- erase, block-erase, sector-erase, byte-program, byte- verify, prog-sb1, prog-sb2, prog-sb3, prog-sc0, prog- sc1, select-block0, select-block1. see table 4-1 for all signal logic assignments, figure 4-1 for i/o pin assign- ments, and table 14-11 for the timing parameters. the criti- cal timing for all erase and program commands is generated by an on-chip flash memory controller. the high- to-low transition of the prog# signal initiates the erase or program commands, which are synchronized internally. the read commands are asynchronous reads, indepen- dent of the prog# signal level. a detailed description of the external host mode com- mands follows. the select-block0 command enables block 0 to be pro- grammed in external host mode. once this command is executed, all subsequent external host commands will be directed at block 0. see figure 14-15 for timing waveforms. the select-block1 command enables block 1 (8 kbyte block) to be programmed. once this command is exe- cuted, all subsequent external host commands that are directed to the address range below 2000h will be directed at block 1. the select-block1 command only affects the lowest 8 kbyte of the program address space. for addresses greater than or equal to 2000h, block 0 is accessed by default. upon entering external host mode, block 1 is selected by default. the chip-erase, block-erase, and sector-erase com- mands are used for erasing all or part of the memory array. erased data bytes in the memory array will be erased to ffh. memory locations that are to be programmed must be in the erased state prior to programming. the chip-erase command erases all bytes in both memory blocks, regardless of any previous select-block0 or select- block1 commands. chip-erase ignores the security lock status and will erase the security lock, returning the device to its unlocked state. the chip-erase command will also erase the sc0 bit. upon completion of the chip-erase command, block 1 will be the selected block. see figure 14-16 for timing waveforms. the block-erase command erases all bytes in the selected memory blocks. this command will not be executed if the security lock is enabled. the selection of the memory block to be erased is determined by the prior execution select- block0 or select-block1 command. see figure 14-18 for the timing waveforms. the sector-erase command erases all of the bytes in a sector. the sector size for the flash memory is 128 bytes. this command will not be executed if the security lock is enabled. see figure 14-19 for timing waveforms. the byte-program command is used for programming new data into the memory array. programming will not take place if any security locks are enabled. see figure 14-20 for timing waveforms. the byte-verify command allows the user to verify that the device correctly performed an erase or program com- mand. this command will be disabled if any security locks are enabled. see figure 14-23 for timing waveforms. table 4-3: p roduct i dentification address data manufacturer?s id 30h bfh device id sst89e52rd2 31h 9ch sst89v52rd2 31h 9dh sst89e54rd2 31h 9eh sst89v54rd2 31h 9fh sst89e58rd2 31h 9bh sst89v58rd2 31h 9ah sst89e516rd2 31h 92h sst89v516rd2 31h 93h t4-3.0 1255
38 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 the prog-sb1, prog-sb2, prog-sb3 commands program the security bits, the functions of these bits are described in the security lock section and also in table 9-1. once pro- grammed, these bits can only be erased through a chip- erase command. see figure 14-21 for timing waveforms. prog-sc0 command programs sc0 bit, which determines the state of sfcf[0] out of reset. once programmed, sc0 can only be restored to an erased state via a chip-erase command. see figure 14-22 for timing waveforms. prog-sc1 command programs sc1 bit, which determines the state of sfcf[1] out of reset. once programmed, sc1 can only be restored to an erased state via a chip-erase command. see figure 14-22 for timing waveforms. 4.1.4 external host mode clock source in external host mode, an internal oscillator will provide clocking for the device, and the oscillator is unaffected by the clock doubler logic. the on-chip oscillator will be turned on as the device enters external host mode; i.e. when psen# goes low while rst is high. during external host mode, the cpu core is held in reset. upon exit from exter- nal host mode, the internal oscillator is turned off. 4.1.5 flash operation status detection via external host handshake the device provides two methods for an external host to detect the completion of a flash memory operation to opti- mize the program or erase time. the end of a flash mem- ory operation cycle can be detected by: 1. monitoring the ready/busy# bit at p3[3]; 2. monitoring the data# polling bit at p0[3]. 4.1.5.1 ready/busy# (p3[3]) the progress of the flash memory programming can be monitored by the ready/busy# output signal. p3[3] is driven low, some time after ale/prog# goes low during a flash memory operation to indicate the busy# status of the flash control unit (fcu). p3[3] is driven high when the flash programming operation is completed to indicate the ready status. 4.1.5.2 data# polling (p0[3]) during a program operation, any attempts to read (byte- verify), while the device is busy, will receive the comple- ment of the data of the last byte loaded (logic low, i.e. ?0? for an erase) on p0[3] with the rest of the bits ?0?. during a program operation, the byte-verify command is reading the data of the last byte loaded, not the data at the address specified. 4.1.6 instructions to perform external host mode commands to program data into the memory array, apply power supply voltage (v dd ) to v dd and rst pins, and per- form the following steps: 1. maintain rst high and set psen# from logic high to low, in sequence according to the appropriate timing diagram. 2. raise ea# high (v ih ). 3. issue read-id command to enable the external host mode. 4. verify that the memory blocks or sectors for pro- gramming is in the erased state, ffh. if they are not erased, then erase them using the appropriate erase command. 5. select the memory location using the address lines (p3[5:4], p2[5:0], p1[7:0]). 6. present the data in on p0[7:0]. 7. pulse ale/prog#, observing minimum pulse width. 8. wait for low to high transition on ready/busy# (p3[3]). 9. repeat steps 5 - 8 until programming is finished. 10. verify the flash memory contents. 4.1.7 additional read commands in external host mode the procedure to issue additional read commands, shown in table 4-4 below, is the same as the read id command format, only the address is changed. here is a short list of useful features: read the status of the security bits (sb1_i, sb2_i, sb3_i). read the configuration bits (sc0_i, sc1_i) status. read the clock mode (edc_i) status. note: commands shown in table 4-4 are not the arming type.
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 39 ?2004 silicon storage technology, inc. s71255-00-000 3/04 x = don?t care 4.2 in-application programming mode the device offers either 16/24/40/72 kbyte of in-application programmable flash memory. during in-application pro- gramming, the cpu of the microcontroller enters iap mode. the two blocks of flash memory allow the cpu to execute user code from one block, while the other is being erased or reprogrammed concurrently. the cpu may also fetch code from an external memory while all internal flash is being reprogrammed. the mailbox registers (sfst, sfcm, sfal, sfah, sfdt and sfcf) located in the spe- cial function register (sfr), control and monitor the device?s erase and program process. table 4-6 and table 4-7 outline the commands and their associated mailbox register settings. 4.2.1 in-application programming mode clock source during iap mode, both the cpu core and the flash control- ler unit are driven off the external clock. however, an inter- nal oscillator will provide timing references for program and erase operations. the internal oscillator is only turned on when required, and is turned off as soon as the flash oper- ation is completed. 4.2.2 memory bank selection for in-application programming mode with the addressing range limited to 16 bit, only 64 kbyte of program address space is ?visible? at any one time. as shown in table 4-5, the bank selection (the configuration of ea# and sfcf[1:0]), allows block 1 memory to be overlaid on the lowest 8 kbyte of block 0 memory, making block 1 reachable. the same concept is employed to allow both block 0 and block 1 flash to be accessible to iap opera- tions. code from a block that is not visible may not be used as a source to program another address. however, a block that is not ?visible? may be programmed by code from the other block through mailbox registers. the device allows iap code in one block of memory to pro- gram the other block of memory, but may not program any location in the same block. if an iap operation originates physically from block 0, the target of this operation is implic- itly defined to be in block 1. if the iap operation originates physically from block 1, then the target address is implicitly defined to be in block 0. if the iap operation originates from external program space, then, the target will depend on the address and the state of bank selection. 4.2.3 iap enable bit the iap enable bit, sfcf[6], enables in-application pro- gramming mode. until this bit is set, all flash programming iap commands will be ignored. table 4-4: a dditional r ead c ommands in e xternal h ost m ode address data 60h x x x sc1_i sc0_i sb1_i sb2_i sb3_i 61h xxxxxxedc_ix t4-4.0 1255 table 4-5: iap a ddress r esolution for sst89e/v516rd2 ea# sfcf[1:0] address of iap inst. tar get address block being programmed 1 00 >= 2000h (block 0) >= 2000h (block 0) none 1 1. no operation is performed because code from one bloc k may not program the same originating block 1 00 >= 2000h (block 0) < 2000h (block 1) block 1 1 00 < 2000h (block 1) any (block 0) block 0 1 01, 10, 11 any (block 0) >= 2000h (block 0) none 1 1 01, 10, 11 any (block 0) < 2000h (block 1) block 1 0 00 from external >= 2000h (block 0) block 0 0 00 from external < 2000h (block 1) block 1 0 01, 10, 11 from external any (block 0) block 0 t4-5.0 1255
40 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 4.2.4 in-application programming mode commands all of the following commands can only be initiated in the iap mode. in all situations, writing the control byte to the sfcm register will initiate all of the operations. all com- mands will not be enabled if the security locks are enabled on the selected memory block. the program command is for programming new data into the memory array. the portion of the memory array to be programmed should be in the erased state, ffh. if the memory is not erased, it should first be erased with an appropriate erase command. warning: do not attempt to write (program or erase) to a block that the code is cur- rently fetching from. this will cause unpredictable pro- gram behavior and may corrupt program data. 4.2.4.1 chip-erase the chip-erase command erases all bytes in both memory blocks. this command is only allowed when ea#=0 (exter- nal memory execution). additionally this command is not permitted when the device is in level 4 locking. in all other instances, this command ignores the security lock status and will erase the security lock bits and re-map bits. 4.2.4.2 block-erase the block-erase command erases all bytes in one of the two memory blocks (block 0 or block 1). the selection of the memory block to be erased is determined by the (sfah[7]) of the superflash address register. for sst89x516rd2, refer to table 4-5. for sst89x5xrd2, if sfah[7] = 0b, the primary flash memory block 0 is selected. if sfah[7:4] = eh, the secondary flash memory block 1 is selected. the block-erase command sequence for sst89x5xrd2 is as follows: 4.2.4.3 sector-erase the sector-erase command erases all of the bytes in a sector. the sector size for the flash memory blocks is 128 bytes. the selection of the sector to be erased is deter- mined by the contents of sfah and sfal. set-up mov sfdt, #55h interrupt scheme mov sfcm, #81h polling scheme mov sfcm, #01h int1 interrupt indicates completion sfst[2] indicates operation completion iap enable orl sfcf, #40h 1255 f08.0 set-up mov sfdt, #55h iap enable orl sfcf, #40h or interrupt scheme mov sfcm, #8dh polling scheme mov sfcm, #0dh erase block 1 mov sfah, #f0h erase block 0 mov sfah, #00h int1 interrupt indicates completion sfst[2] indicates operation completion 1255 f09.0 program sector address mov sfah, #sector_addressh mov sfal, #sector_addressl interrupt scheme mov sfcm, #8bh polling scheme mov sfcm, #0bh int1 interrupt indicates completion sfst[2] indicates operation completion 1255 f10.0 iap enable orl sfcf, #40h
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 41 ?2004 silicon storage technology, inc. s71255-00-000 3/04 4.2.4.4 byte-program the byte-program command programs data into a single byte. the address is determined by the contents of sfah and sfal. the data byte is in sfdt. 4.2.4.5 byte-verify the byte-verify command allows the user to verify that the device has correctly performed an erase or program com- mand. byte-verify command returns the data byte in sfdt if the command is successful. the user is required to check that the previous flash operation has fully completed before issuing a byte-verify. byte-verify command execution time is short enough that there is no need to poll for command completion and no interrupt is generated. 4.2.4.6 prog-sb3, prog-sb2, prog-sb1 prog-sb3, prog-sb2, prog-sb1 commands are used to program the security bits (see table 9-1). completion of any of these commands, the security options will be updated immediately. security bits previously in un-programmed state can be programmed by these commands. prog-sb3, prog-sb2 and prog-sb1 commands should only reside in block 1 or external code memory. move data to sfdt mov sfdt, #data interrupt scheme mov sfcm, #8eh polling scheme mov sfcm, #0eh int1 interrupt indicates completion sfst[2] indicates operation completion program byte address mov sfah, #byte_addressh mov sfal, #byte_addressl 1255 f11.0 iap enable orl sfcf, #40h mov sfcm, #0ch sfdt register contains data program byte address mov sfah, #byte_addressh mov sfal, #byte_addressl 1255 f12.0 iap enable orl sfcf, #40h set-up mov sfdt, #0aah or or int1# interrupt indicates completion polling sfst[2] indicates completion program sb2 mov sfcm, #03h or mov sfcm, #83h program sb1 mov sfcm, #0fh or mov sfcm, #8fh program sb3 mov sfcm, #05h or mov sfcm, #85h 1255 f13.0 iap enable orl sfcf, #40h
42 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 4.2.4.7 prog-sc0, prog-sc1 prog-sc0 command is used to program the sc0 bit. this command only changes the sc0 bit and has no effect on bsel bit until after a reset cycle. sc0 bit previously in un-programmed state can be pro- grammed by this command. the prog-sc0 command should reside only in block 1 or external code memory. prog-sc1 command is used to program the sc1 bit. this command only changes the sc1 bit and has no effect on sfcf[1] bit until after a reset cycle. sc1 bit previously in un-programmed state can be pro- grammed by this command. the prog-sc1 command should reside only in block 1 or external code memory. 4.2.4.8 enable-clock-double enable-clock-double command is used to make the mcu run at 6 clocks per machine cycle. the standard (default) is 12 clocks per machine cycle (i.e. clock double command disabled). there are no iap counterparts for the external host com- mands select-block0 and select-block1. 4.2.5 polling a command that uses the polling method to detect flash operation completion should poll on the flash_busy bit (sfst[2]). when flash_busy de-asserts (logic 0), the device is ready for the next operation. movc instruction may also be used for verification of the programming and erase operation of the flash memory. movc instruction will fail if it is directed at a flash block that is still busy. 4.2.6 interrupt termination if interrupt termination is selected, (sfcm[7] is set), then an interrupt (int1) will be generated to indicate flash opera- tion completion. under this condition, the int1 becomes an internal interrupt source. the int1# pin can now be used as a general purpose port pin and it cannot be the source of external interrupt 1 during in-application programming. in order to use an interrupt to signal flash operation termi- nation. ex1 and ea bits of ie register must be set. the it1 bit of tcon register must also be set for edge trigger detection. . program sc0 or sc1 - interrupt scheme mov sfcm, #89h program sc0 or sc1 - polling scheme mov sfcm, #09h int1# interrupt indicates completion polling sfst[2] indicates completion 1255 f14.0 iap enable orl sfcf, #40h set-up program sc1 mov sfah, #0aah mov sfdt, #0aah set-up program sc0 mov sfah, #5ah mov sfdt, #0aah program enable-clock-double interrupt scheme mov sfcm, #88h program enable-clock-double polling scheme mov sfcm, #08h int1# interrupt indicates completion polling sfst[2] indicates completion 1255 f15.0 iap enable orl sfcf, #40h set-up enable-clock-double mov sfah, #55h mov sfdt, #0aah
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 43 ?2004 silicon storage technology, inc. s71255-00-000 3/04 note: disiapl pin in plcc or tqfp will also disable iap commands if it is externally pulled low when reset. note: disiapl pin in plcc or tqfp will also disable iap commands if it is externally pulled low when reset. table 4-6: iap c ommands 1 for sst89e/v516rd2 operation sfcm [6:0] 2 sfdt [7:0] sfah [7:0] sfal [7:0] chip-erase 3 01h 55h x 4 x block-erase 5 0dh 55h ah x sector-erase 5 0bh x ah 6 al 7 byte-program 5 0eh di 8 ah al byte-verify (read) 5 0ch do 8 ah al prog-sb1 9 0fh aah x x prog-sb2 9 03h aah x x prog-sb3 9 05h aah x x prog-sc0 9 09h aah 5ah x enable-clock-double 9 08h aah 55h x t4-6.0 1255 1. sfcf[6]=1 enables iap commands; sfcf[6]=0 disables iap commands. 2. interrupt/polling enable for flash operation completion sfcm[7] =1: interrupt enable for flash operation completion 0: polling enable for flash operation completion 3. chip-erase only functions in iap mode when ea#=0 (external memory execution) and device is not in level 4 locking. 4. x can be v il or v ih , but no other value. 5. refer to table 4-5 for address resolution 6. ah = address high order byte 7. al = address low order byte 8. di = data input, do = data output, all other values are in hex. 9. instruction must be located in block 1 or external code memory. table 4-7: iap c ommands 1 for sst89e/v5 x rd2 1. sfcf[6]=1 enables iap commands; sfcf[6]=0 disables iap commands. operation sfcm [6:0] 2 2. interrupt/polling enable for flash operation completion sfcm[7] =1: interrupt enable for flash operation completion 0: polling enable for flash operation completion sfdt [7:0] sfah [7:0] sfal [7:0] chip-erase 3 3. chip-erase only functions in iap mode when ea#=0 (external memory execution) and device is not in level 4 locking. 01h 55h x 4 4. x can be v il or v ih , but no other value. x block-erase 0dh 55h ah 5 5. ah = address high order byte x sector-erase 0bh x ah al 6 6. al = address low order byte byte-program 0eh di 7 7. di = data input, do = data output, all other values are in hex. ah al byte-verify (read) 8 8. sfah[7:5] = 111b selects block 1, sfah[7] = 0b selects block 0 0ch do 7 ah al prog-sb1 9 9. instruction must be located in block 1 or external code memory. 0fh aah x x prog-sb2 9 03h aah x x prog-sb3 9 05h aah x x prog-sc0 9 09h aah 5ah x prog-sc1 9 09h aah aah x enable-clock-double 9 08h aah 55h x t4-7.0 1255
44 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 5.0 timers/counters 5.1 timers the device has three 16-bit registers that can be used as either timers or event counters. the three timers/counters are denoted timer 0 (t0), timer 1 (t1), and timer 2 (t2). each is designated a pair of 8-bit registers in the sfrs. the pair consists of a most significant (high) byte and least significant (low) byte. the respective registers are tl0, th0, tl1, th1, tl2, and th2. 5.2 timer set-up refer to table 3-10 for tmod, tcon, and t2con regis- ters regarding timers t0, t1, and t2. the following tables provide tmod values to be used to set up timers t0, t1, and t2. except for the baud rate generator mode, the values given for t2con do not include the setting of the tr2 bit. there- fore, bit tr2 must be set separately to turn the timer on. table 5-1: t imer /c ounter 0 mode function tmod internal control 1 1. the timer is turned on/off by setting/clearing bit tr0 in the software. external control 2 2. the timer is turned on/off by the 1 to 0 transition on int0# (p3.2) when tr0 = 1 (hardware control). used as timer 0 13-bit timer 00h 08h 1 16-bit timer 01h 09h 2 8-bit auto-reload 02h 0ah 3 two 8-bit timers 03h 0bh used as counter 0 13-bit timer 04h 0ch 1 16-bit timer 05h 0dh 2 8-bit auto-reload 06h 0eh 3 two 8-bit timers 07h 0fh t5-1.0 1255 table 5-2: t imer /c ounter 1 mode function tmod internal control 1 external control 2 used as timer 0 13-bit timer 00h 80h 1 16-bit timer 10h 90h 2 8-bit auto-reload 20h a0h 3 does not run 30h b0h used as counter 0 13-bit timer 40h c0h 1 16-bit timer 50h d0h 2 8-bit auto-reload 60h e0h 3 not available - - t5-2.0 1255 1. the timer is turned on/off by setting/clearing bit tr1 in the software. 2. the timer is turned on/off by the 1 to 0 transition on int1# (p3.3) when tr1 = 1 (hardware control). table 5-3: t imer /c ounter 2 mode t2con internal control 1 1. capture/reload occurs only on timer/counter overflow. external control 2 2. capture/reload occurs on timer/counter overflow and a 1 to 0 transition on t2ex (p1.1) pin except when timer 2 is used in the baud rate generating mode. used as timer 16-bit auto-reload 00h 08h 16-bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h used as counter 16-bit auto-reload 02h 0ah 16-bit capture 03h 0bh t5-3.0 1255
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 45 ?2004 silicon storage technology, inc. s71255-00-000 3/04 5.3 programmable clock-out a 50% duty cycle clock can be programmed to come out on p1.0. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50% duty cycle clock ranging from 122 hz to 8 mhz at a 16 mhz operating frequency (61 hz to 4 mhz in 12 clock mode). to configure timer/counter 2 as a clock generator, bit c/#t2 (in t2con) must be cleared and bit t20e in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator fre- quency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in this equation: oscillator frequency n x (65536 - rcap2h, rcap2l) n = 2 (in 6 clock mode) 4 (in 12 clock mode) where (rcap2h, rcap2l) = the contents of rcap2h and rcap2l taken as a 16-bit unsigned integer. in the clock-out mode, timer 2 roll-overs will not generate an interrupt. this is similar to when it is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate gen- erator and a clock generator simultaneously. note, how- ever, that the baud-rate and the clock-out frequency will not be the same. 6.0 serial i/o 6.1 full-duplex, enhanced uart the device serial i/o port is a full-duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respec- tively, while the software is performing other tasks. the transmit and receive registers are both located in the serial data buffer (sbuf) special function register. writ- ing to the sbuf register loads the transmit register, and reading from the sbuf register obtains the contents of the receive register. the uart has four modes of operation which are selected by the serial port mode specifier (sm0 and sm1) bits of the serial port control (scon) special function register. in all four modes, transmission is initiated by any instruction that uses the sbuf register as a destination register. reception is initiated in mode 0 when the receive interrupt (ri) flag bit of the serial port control (scon) sfr is cleared and the reception enable/ disable (ren) bit of the scon register is set. reception is initiated in the other modes by the incoming start bit if the ren bit of the scon register is set. 6.1.1 framing error detection framing error detection is a feature, which allows the receiving controller to check for valid stop bits in modes 1, 2, or 3. missing stops bits can be caused by noise in serial lines or from simultaneous transmission by two cpus. framing error detection is selected by going to the pcon register and changing smod0 = 1 (see figure 6-1). if a stop bit is missing, the framing error bit (fe) will be set. software may examine the fe bit after each reception to check for data errors. after the fe bit has been set, it can only be cleared by software. valid stop bits do not clear fe. when fe is enabled, ri rises on the stop bit, instead of the last data bit (see figure 6-2 and figure 6-3). figure 6-1: f raming e rror b lock d iagram 1255 f16.0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri smod0 smod1 pof gf1 gf0 pd idl scon (98h) pcon (87h) set fe bit if stop bit is 0 (framing error) (smod0 = 1) sm0 to uart mode control (smod0 = 0) to uart framing error control bof
46 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 6-2: uart t imings in m ode 1 figure 6-3: uart t imings in m odes 2 and 3 start bit rxd ri smod0=x fe smod0=1 d0 d1 d2 d3 d4 d5 d6 d7 data byte stop bit 1255 f17.0 start bit rxd ri smod0=1 fe smod0=1 ri smod0=0 d0 d1 d2 d3 d4 d5 d6 d7 d8 data byte ninth bit stop bit 1255 f18.0
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 47 ?2004 silicon storage technology, inc. s71255-00-000 3/04 6.1.2 automatic address recognition automatic address recognition helps to reduce the mcu time and power required to talk to multiple serial devices. each device is hooked together sharing the same serial link with its own address. in this configuration, a device is only interrupted when it receives its own address, thus eliminating the software overhead to compare addresses. this same feature helps to save power because it can be used in conjunction with idle mode to reduce the system?s overall power consumption. since there may be multiple slaves hooked up serial to one master, only one slave would have to be interrupted from idle mode to respond to the master?s transmission. automatic address recognition (aar) allows the other slaves to remain in idle mode while only one is interrupted. by limiting the number of interrup- tions, the total current draw on the system is reduced. there are two ways to communicate with slaves: a group of them at once, or all of them at once. to communicate with a group of slaves, the master sends out an address called the given address. to communicate with all the slaves, the master sends out an address called the ?broadcast? address. aar can be configured as mode 2 or 3 (9-bit modes) and setting the sm2 bit in scon. each slave has its own sm2 bit set waiting for an address byte (9th bit = 1). the receive interrupt (ri) flag will only be set when the received byte matches either the given address or the broadcast address. next, the slave then clears its sm2 bit to enable reception of the data bytes (9th bit = 0) from the master. when the 9th bit = 1, the master is sending an address. when the 9th bit = 0, the master is sending actual data. if mode 1 is used, the stop bit takes the place of the 9th bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. note that mode 0 cannot be used. set- ting sm2 bit in the scon register in mode 0 will have no effect. each slave?s individual address is specified by sfr saddr. sfr saden is a mask byte that defines ?don?t care? bits to form the given address when combined with saddr. see the example below: 6.1.2.1 using the given address to select slaves any bits masked off by a 0 from saden become a ?don?t care? bit for the given address. any bit masked off by a 1, becomes anded with saddr. the ?don?t cares? provide flexibility in the user-defined addresses to address more slaves when using the given address. shown in the example above, slave 1 has been given an address of 1111 0001 (saddr). the saden byte has been used to mask off bits to a given address to allow more combinations of selecting slave 1 and slave 2. in this case for the given addresses, the last bit (lsb) of slave 1 is a ?don?t care? and the last bit of slave 2 is a 1. to communi- cate with slave 1 and slave 2, the master would need to send an address with the last bit equal to 1 (e.g. 1111 0001) since slave 1?s last bit is a don?t care and slave 2?s last bit has to be a 1. to communicate with slave 1 alone, the master would send an address with the last bit equal to 0 (e.g. 1111 0000), since slave 2?s last bit is a 1. see the table below for other possible combinations. if the user added a third slave such as the example below: slave 1 saddr = 1111 0001 saden = 1111 1010 given = 1111 0x0x slave 2 saddr = 1111 0011 saden = 1111 1001 given = 1111 0xx1 select slave 1 only slave 1 given address possible addresses 1111 0x0x 1111 0000 1111 0100 select slave 2 only slave 2 given address possible addresses 1111 0xx1 1111 0111 1111 0011 select slaves 1 & 2 slaves 1 & 2 possible addresses 1111 0001 1111 0101 slave 3 saddr = 1111 1001 saden = 1111 0101 given = 1111 x0x1
48 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 the user could use the possible addresses above to select slave 3 only. another combination could be to select slave 2 and 3 only as shown below. more than one slave may have the same saddr address as well, and a given address could be used to modify the address so that it is unique. 6.1.2.2 using the broadcast address to select slaves using the broadcast address, the master can communicate with all the slaves at once. it is formed by performing a logi- cal or of saddr and saden with ?0?s in the result treated as ?don?t cares?. ?don?t cares? allow for a wider range in defining the broad- cast address, but in most cases, the broadcast address will be ffh. on reset, saddr and saden are ?0?. this produces an given address of all ?don?t cares? as well as a broadcast address of all ?don?t cares.? this effectively disables auto- matic addressing mode and allows the microcontroller to function as a standard 8051, which does not make use of this feature. 6.2 serial peripheral interface 6.2.1 spi features master or slave operation 10 mhz bit frequency (max) lsb first or msb first data transfer four programmable bit rates end of transmission (spif) write collision flag protection (wcol) wake up from idle mode (slave mode only) 6.2.2 spi description the serial peripheral interface (spi) allows high-speed syn- chronous data transfer between the sst89e/v554a and peripheral devices or between several sst89e/v554a devices. figure 6-4 shows the correspondence between master and slave spi devices. the sck pin is the clock output and input for the master and slave modes, respectively. the spi clock generator will start following a write to the master devices spi data register. the written data is then shifted out of the mosi pin on the master device into the mosi pin of the slave device. following a complete transmission of one byte of data, the spi clock generator is stopped and the spif flag is set. an spi interrupt request will be gener- ated if the spi interrupt enable bit (spie) and the serial port interrupt enable bit (es) are both set. an external master drives the slave select input pin, ss#/ p1[4], low to select the spi module as a slave. if ss#/p1[4] has not been driven low, then the slave spi unit is not active and the mosi/p1[5] port can also be used as an input port pin. cpha and cpol control the phase and polarity of the spi clock. figures 6-5 and 6-6 show the four possible combina- tions of these two bits. figure 6-4: spi m aster - slave i nterconnection select slave 3 only slave 2 given address possible addresses 1111 x0x1 1111 1011 1111 1001 select slaves 2 & 3 only slaves 2 & 3 possible addresses 1111 0011 slave 1 1111 0001 = saddr +1111 1010 = saden 1111 1x11 = broadcast 1255 f19.0 8-bit shift register msb master lsb spi clock generator miso miso mosi mosi sck sck ss# ss# 8-bit shift register msb slave lsb v ss v dd
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 49 ?2004 silicon storage technology, inc. s71255-00-000 3/04 6.2.3 spi transfer formats figure 6-5: spi t ransfer f ormat with cpha = 0 figure 6-6: spi t ransfer f ormat with cpha = 1 1255 f20.0 msb sck cycle # (for reference) sck (cpol=0) sck (cpol=1) mosi (from master) miso (from slave) ss# (to slave) 6 12345678 5 msb 654321lsb 4 3 2 1 lsb 1255 f21.0 msb sck cycle # (for reference) sck (cpol=0) sck (cpol=1) mosi (from master) miso (from slave) ss# (to slave) 6 12345678 5 msb654321 lsb 4 3 2 1 lsb
50 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 7.0 watchdog timer the device offers a programmable watchdog timer (wdt) for fail safe protection against software deadlock and auto- matic recovery. to protect the system against software deadlock, the user software must refresh the wdt within a user-defined time period. if the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (wdre= 1). the software can be designed such that the wdt times out if the program does not work properly. the wdt in the device uses the system clock (xtal1) as its time base. so strictly speaking, it is a watchdog counter rather than a watchdog timer. the wdt register will incre- ment every 344,064 crystal clocks. the upper 8-bits of the time base register (wdtd) are used as the reload register of the wdt. the wdts flag bit is set by wdt overflow and is not changed by wdt reset. user software can clear wdts by writing ?1? to it. figure 7-1 provides a block diagram of the wdt. two sfrs (wdtc and wdtd) control watchdog timer operation. during idle mode, wdt operation is temporarily sus- pended, and resumes upon an interrupt exit from idle. the time-out period of the wdt is calculated as follows: period = (255 - wdtd) * 344064 * 1/f clk (xtal1) where wdtd is the value loaded into the wdtd register and f osc is the oscillator frequency. figure 7-1: b lock d iagram of p rogrammable w atchdog t imer 1255 f22.0 wdt upper byte wdt reset internal reset 344064 clks counter clk (xtal1) ext. rst wdtc wdtd
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 51 ?2004 silicon storage technology, inc. s71255-00-000 3/04 8.0 programmable counter array the programmable counter array (pca) present on the sst89e/v5xrd2 is a special 16-bit timer that has five 16- bit capture/compare modules. each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. the 5th module can be pro- grammed as a watchdog timer in addition to the other four modes. each module has a pin associated with it in port 1. module 0 is connected to p1.3 (cex0), module 1 to p1[4] (cex1), module 2 to p1[5] (cex2), module 3 to p1[6] (cex3), and module 4 to p1[7] (cex4). pca configuration is shown in figure 8-1. 8.1 pca overview pca provides more timing capabilities with less cpu inter- vention than the standard timer/counter. its advantages include reduced software overhead and improved accuracy. the pca consists of a dedicated timer/counter which serves as the time base for an array of five compare/cap- ture modules. figure 8-1 shows a block diagram of the pca. external events associated with modules are shared with corresponding port 1 pins. modules not using the port pins can still be used for standard i/o. each of the five modules can be programmed in any of the following modes: rising and/or falling edge capture software timer high speed output watchdog timer (module 4 only) pulse width modulator (pwm) 8.2 pca timer/counter the pca timer is a free-running 16-bit timer consisting of registers ch and cl (the high and low bytes of the count values). the pca timer is common time base for all five modules and can be programmed to run at: 1/6 the oscilla- tor frequency, 1/2 the oscillator frequency, timer 0 overflow, or the input on the eci pin (p1.2). the timer/counter source is determined from the cps1 and cps0 bits in the cmod sfr as follows (see ?pca timer/counter mode register (cmod)? on page 28): figure 8-1: pca t imer /c ounter and c ompare /c apture m odules table 8-1: pca t imer /c ounter s ource cps1 cps0 12 clock mode 6 clock mode 00 f osc /12 f osc /6 01 f osc /4 f osc /2 1 0 timer 0 overflow timer 0 overflow 1 1 external clock at eci pin (maximum rate = f osc /8) external clock at eci pin (maximum rate = f osc /4) t8-1.0 1255 module 0 module 1 module 2 module 3 module 4 pca timer/counter 1255 f23.0 p1.7/cex4 p1.6/cex3 p1.5/cex2 p1.4/cex1 p1.3/cex0 16 bits 16 bits each
52 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 the table below summarizes various clock inputs at two common frequencies. the four possible cmod timer modes with and without the overflow interrupt enabled are shown below. this list assumes that pca will be left running during idle mode. the ccon register is associated with all pca timer functions. it contains run control bits and flags for the pca timer (cf) and all modules. to run the pca the cr bit (ccon.6) must be set by software. clearing the bit, will turn off pca. when the pca counter overflows, the cf (ccon.7) will be set, and an interrupt will be generated if the ecf bit in the cmod register is set. the cf bit can only be cleared by software. each module has its own timer interrupt or capture interrupt flag (ccf0 for module 0, ccf4 for module 4, etc.). they are set when either a match or capture occurs. these flags can only be cleared by software. (see ?pca timer/counter control register (ccon)? on page 27.) table 8-2: pca t imer /c ounter i nputs pca timer/counter mode clock increments 12 mhz 16 mhz mode 0: f osc /12 1 sec 0.75 sec mode 1: 330 nsec 250 nsec mode 2: timer 0 overflows 1 1. in mode 2, the overflow interrupt for timer 0 does not need to be enabled. timer 0 programmed in: 8-bit mode 256 sec 192 sec 16-bit mode 65 msec 49 sec 8-bit auto-reload 1 to 255 sec 0.75 to 191 sec mode 3: external input max 0.66 sec 0.50 sec t8-2.0 1255 table 8-3: cmod v alues pca count pulse selected cmod value without interrupt enabled with interrupt enabled internal clock, f osc /12 00h 01h internal clock, f osc /4 02h 03h timer 0 overflow 04h 05h external clock at p1.2 06h 07h t8-3.0 1255
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 53 ?2004 silicon storage technology, inc. s71255-00-000 3/04 8.3 compare/capture modules each pca module has an associated sfr with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. refer to ?pca compare/capture module mode reg- ister (ccapmn)? on page 29 for details. the registers each contain 7 bits which are us ed to control the mode each module will operate in. the eccf bit (ccapmn.0 where n = 0, 1, 2, 3, or 4 depending on module) will enable the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set, causes the cex output associated with the mod- ule to toggle when there is a match between the pca counter and the module?s capture/compare register. when there is a match between the pca counter and the mod- ule?s capture/compare register, the matn (ccapmn.3) and the ccfn bit in the ccon register to be set. bits capn (ccapmn.4) and capp (ccapmn.5) deter- mine whether the capture input will be active on a positive edge or negative edge. the capn bit enables the negative edge that a capture input will be active on, and the capp bit enables the positive edge. when both bits are set, both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set, enables the comparator function. table 8-5 shows the ccapmn settings for the various pca functions. there are two additional register associated with each of the pca modules: ccapnh and ccapnl. they are regis- ters that hold the 16-bit count value when a capture occurs or a compare occurs. when a module is used in pwm mode, these registers are used to control the duty cycle of the output. see figure 8-1. table 8-4: pca h igh and l ow r egister c ompare /c apture m odules symbol description direct address bit address, symbol, or alternative port function reset value msb lsb ccap0h pca module 0 compare/capture registers fah ccap0h[7:0] 00h ccap0l eah ccap0l[7:0] 00h ccap1h pca module 1 compare/capture registers fbh ccap1h[7:0] 00h ccap1l ebh ccap1l[7:0] 00h ccap2h pca module 2 compare/capture registers fch ccap2h[7:0] 00h ccap2l ech ccap2l[7:0] 00h ccap3h pca module 3 compare/capture registers fdh ccap3h[7:0] 00h ccap3l edh ccap3l[7:0] 00h ccap4h pca module 4 compare/capture registers feh ccap4h[7:0] 00h ccap4l eeh ccap4l[7:0] 00h t8-4.0 1255
54 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 8-5: pca m odule m odes without interrupt enabled - 1 ecomy 2 cappy 2 capny 2 maty 2 togy 2 pwmy 2 eccfy 2 module code - 0 0 0 0 0 0 0 no operation - 0 1 0 0 0 0 0 16-bit capture on positive-edge trigger at cex[4:0] - 0 0 1 0 0 0 0 16-bit capture on negative-edge trigger at cex[4:0] - 0 1 1 0 0 0 0 16-bit capture on positive/negative-edge trigger at cex[4:0] - 1 0 0 1 0 0 0 compare: software timer - 1 0 0 1 1 0 0 compare: high-speed output - 1 0 0 0 0 1 0 compare: 8-bit pwm -1 0 0 10 or 1 3 0 0 compare: pca wdt (ccapm4 only) 4 t8-5.0 1255 1. user should not write ?1?s to reserved bits. the value read from a reserved bit is indeterminate. 2. y = 0, 1, 2, 3, 4 3. a 0 disables toggle function. a 1 enables toggle function on cex[4:0] pin. 4. for pca wdt mode, also set the wdte bit in the cmod register to enable the reset output signal. table 8-6: pca m odule m odes with interrupt enabled - 1 1. user should not write ?1?s to reserved bits. the value read from a reserved bit is indeterminate. ecomy 2 2. y = 0, 1, 2, 3, 4 cappy 2 capny 2 maty 2 togy 2 pwmy 2 eccfy 2 module code - 0 1 0 0 0 0 1 16-bit capture on positive-edge trigger at cex[4:0] - 0 0 1 0 0 0 1 16-bit capture on negative-edge trigger at cex[4:0] - 0 1 1 0 0 0 1 16-bit capture on positive/negative-edge trigger at cex[4:0] - 1 0 0 1 0 0 1 compare: software timer - 1 0 0 1 1 0 1 compare: high-speed output -1 0 0 0 0 1 x 3 3. no pca interrupt is needed to generate the pwm. compare: 8-bit pwm -1 0 0 10 or 1 4 4. a 0 disables toggle function. a 1 enables toggle function on cex[4:0] pin. 0x 5 5. enabling an interrupt for the watchdog timer would defeat the purpose of the watchdog timer. compare: pca wdt (ccapm4 only) 6 6. for pca wdt mode, also set the wdte bit in the cmod register to enable the reset output signal. t8-6.0 1255
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 55 ?2004 silicon storage technology, inc. s71255-00-000 3/04 8.3.1 capture mode capture mode is used to capture the pca timer/counter value into a module?s capture registers (ccapnh and ccapnl). the capture will occur on a positive edge, nega- tive edge, or both on the corresponding module?s pin. to use one of the pca modules in the capture mode, either one or both the ccapm bits capn and capp for that module must be set. when a valid transition occurs on the cex pin corresponding to the module used, the pca hard- ware loads the 16-bit value of the pca counter register (ch and cl) into the module?s capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set, then an interrupt will be generated. in the interrupt service rou- tine, the 16-bit capture value must be saved in ram before the next event capture occurs. if a subsequent capture occurred, the original capture values would be lost. after flag event flag has been set by hardware, the user must clear the flag in software. (see figure 8-2) figure 8-2: pca c apture m ode 1255 f24.0 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ecomn cappn capnn matn togn pwmn eccfn ccon ccapmn n=0 to 4 pca interrupt ch cl ccapnh ccapnl pca timer/counter capture cexn 0000
56 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 8.3.2 16-bit software timer mode the 16-bit software timer mode is used to trigger interrupt routines, which must occur at periodic intervals. it is setup by setting both the ecom and mat bits in the module?s ccapmn register. the pca timer will be compared to the module?s capture registers (ccapnl and ccapnh) and when a match occurs, an interrupt will occur, if the ccfn (ccon sfr) and the eccfn ( ccapmn sfr) bits for the module are both set. if necessary, a new 16-bit compare value can be loaded into ccapnh and ccapnl during the interrupt routine. the user should be aware that the hardware temporarily disables the comparator function while these registers are being updated so that an invalid match will not occur. thus, it is recommended that the user write to the low byte first (ccapnl) to disable the comparator, then write to the high byte (ccapnh) to re-enable it. if any updates to the regis- ters are done, the user may want to hold off any interrupts from occurring by clearing the ea bit. (see figure 8-3) figure 8-3: pca c ompare m ode (s oftware t imer ) 1255 f25.0 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ecomn cappn capnn matn togn pwmn eccfn ccon ccapmn n=0 to 4 pca interrupt ch cl ccapnh ccapnl pca timer/counter 0 000 16-bit comparator reset write to ccapnl write to ccapnh 10 enable match
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 57 ?2004 silicon storage technology, inc. s71255-00-000 3/04 8.3.3 high speed output mode the high speed output mode is used to toggle a port pin when a match occurs between the pca timer and the pre- loaded value in the compare registers. in this mode, the cex output pin (on port 1) associated with the pca mod- ule will toggle every time there is a match between the pca counter (ch and cl) and the capture registers (ccapnh and ccapnl). to activate this mode, the user must set tog, mat, and ecom bits in the module?s ccapmn sfr. high speed output mode is much more accurate than tog- gling pins since the toggle occurs before branching to an interrupt. in this case, interrupt latency will not affect the accuracy of the output. when using high speed output, using an interrupt is optional. only if the user wishes to change the time for the next toggle is it necessary to update the compare registers. otherwise, the next toggle will occur when the pca timer rolls over and matches the last compare value. (see figure 8-4) figure 8-4: pca h igh s peed o utput m ode 1255 f26.0 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ecomn cappn capnn matn togn pwmn eccfn ccon ccapmn n=0 to 4 pca interrupt ch cl ccapnh ccapnl pca timer/counter 0 00 16-bit comparator reset write to ccapnl write to ccapnh 10 enable match cexn toggle
58 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 8.3.4 pulse width modulator the pulse width modulator (pwm) mode is used to gener- ate 8-bit pwms by comparing the low byte of the pca timer (cl) with the low byte of the compare register (ccapnl). when cl < ccapnl the output is low. when cl ccapnl the output is high. to activate this mode, the user must set the pwm and ecom bits in the module?s ccapmn sfr. (see figure 8-5 and table 8-7) in pwm mode, the frequency of the output depends on the source for the pca timer. since there is only one set of ch and cl registers, all modules share the pca timer and fre- quency. duty cycle of the output is controlled by the value loaded into the high byte (ccapnh). since writes to the ccapnh register are asynchronous, a new value written to the high byte will not be shifted into ccapnl for compari- son until the next period of the output (when cl rolls over from 255 to 00). to calculate values for ccapnh for any duty cycle, use the following equation: ccapnh = 256(1 - duty cycle) where ccapnh is an 8-bit integer and duty cycle is a fraction. figure 8-5: pca p ulse w idth m odulator m ode table 8-7: p ulse w idth m odulator f requencies pca timer mode pwm frequency 12 mhz 16 mhz 1/12 oscillator frequency 3.9 khz 5.2 khz 1/4 oscillator frequency 11.8 khz 15.6 khz timer 0 overflow: 8-bit 15.5 hz 20.3 hz 16-bit 0.06 hz 0.08 hz 8-bit auto-reload 3.9 khz to 15.3 hz 5.2 khz to 20.3 hz external input (max) 5.9 khz 7.8 khz t8-7.0 1255 1255 f27.0 ecomn cappn capnn matn togn pwmn eccfn ccapmn n=0 to 4 cl ccapnl ccapnh pca timer/counter 0 00 00 8-bit comparator overflow cl < ccapnl cl >= ccapnl enable cexn 0 1
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 59 ?2004 silicon storage technology, inc. s71255-00-000 3/04 8.3.5 watchdog timer the watchdog timer mode is used to improve reliability in the system without increasing chip count (see figure 8-6). watchdog timers are useful for systems that are suscepti- ble to noise, power glitches, or electrostatic discharge. it can also be used to prevent a software deadlock. if during the execution of the user?s code, there is a deadlock, the watchdog timer will time out and an internal reset will occur. only module 4 can be programmed as a watchdog timer (but still can be programmed to other modes if the watchdog timer is not used). to use the watchdog timer, t he user pre-loads a 16-bit value in the compare register. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer, 2. periodically change the pca timer value so it will never match the compare values, or 3. disable the watchdog timer by clearing the wdte bit before a match occurs and then re-enable it. the first two options are more reliable because the watch- dog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not rec- ommended if other pca modules are being used. remem- ber, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most application the first solution is the best option. use the code below to initialize the watchdog timer. mod- ule 4 can be configured in either compare mode, and the wdte bit in cmod must also be set. the user?s software then must periodically change (ccap4h, ccap4l) to keep a match from occurring with the pca timer (ch, cl). this code is given in the watchdog routine below. ;============================================== init_watchdog: movccapm4, #4ch; module 4 in compare mode movccap4l, #0ffh; write to low byte first movccap4h, #0ffh; before pca timer counts up ; to ffff hex, these compare ; values must be changed. orlcmod, #40h; set the wdte bit to enable the ; watchdog timer without ; changing the other bits in ; cmod ;============================================== ;main program goes here, but call watchdog periodically. ;============================================== watchdog: clr ea; hold off interrupts movccap4l, #00; next compare value is within movccap4h, ch; 65,535 counts of the ; current pca setbea; timer value ret ;============================================== this routine should not be part of an interrupt service rou- tine. if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. thus, the purpose of the watchdog would be defeated. instead, call this subroutine from the main program of the pca timer. figure 8-6: pca w atchdog t imer (m odule 4 only ) 1255 f28.0 cidl wdte cps1 cps0 ecf ecomn cappn capnn matn togn pwmn eccfn cmod ccapm4 reset ch cl ccap4h ccap4l pca timer/counter 0 0x0 16-bit comparator reset write to ccap4l write to ccap4h 10 enable match module 4 1x
60 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 9.0 security lock the security lock protects against software piracy and pre- vents the contents of the flash from being read by unautho- rized parties. it also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. there are two different types of security locks in the device security lock system: hard lock and softlock. 9.1 hard lock when hard lock is activated, movc or iap instructions exe- cuted from an unlocked or soft locked program address space, are disabled from reading code bytes in hard locked memory blocks (see table 9-2). hard lock can either lock both flash memory blocks or just lock the 8 kbyte flash memory block (block 1). all external host and iap com- mands except for chip-erase are ignored for memory blocks that are hard locked. 9.2 softlock softlock allows flash contents to be altered under a secure environment. this lock option allows the user to update program code in the soft locked memory block through in- application programming mode under a predetermined secure environment. for example, if block 1 (8k) memory block is locked (hard locked or soft locked), and block 0 memory block is soft locked, code residing in block 1 can program block 0. the following iap mode commands issued through the command mailbox register, sfcm, exe- cuted from a locked (hard locked or soft locked) block, can be operated on a soft locked block: block-erase, sector- erase, byte-program and byte-verify. in external host mode, softlock behaves the same as a hard lock. 9.3 security lock status the three bits that indicate the device security lock status are located in sfst[7:5]. as shown in figure 9- 1 and table 9-1, the three security lock bits control the lock status of the primary and secondary blocks of memory. there are four distinct levels of security lock status. in the first level, none of the security lock bits are programmed and both blocks are unlocked. in the second level, although both blocks are now locked and cannot be programmed, they are available for read operation via byte-verify. in the third level, three differ- ent options are available: block 1 hard lock / block 0 softlock, softlock on both blocks, and hard lock on both blocks. locking both blocks is the same as level 2, block 1 except read operation isn?t available. the fourth level of security is the most secure level. it doesn?t allow read/program of internal memory or boot from external memory. for details on how to program the security lock bits refer to the external host mode and in-application programming sections. figure 9-1: s ecurity l ock l evels note: p = programmed (bit logic state = 0), u = unprogrammed (bit logic state = 1), n = not locked, l = hard locked, s = soft locked level 1 level 2 level 3 level 4 uuu/nn puu/ss upp/ll ppu/ls upu/ss ppp/ll 1255 f29.0 pup/ll upp/ll uup/ls
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 61 ?2004 silicon storage technology, inc. s71255-00-000 3/04 9.4 read operation under lock condition the status of security bits sb1, sb2, and sb3 can be read when the read command is disabled by security lock. there are three ways to read the status. 1. external host mode: read-back = 00h (locked) 2. iap command: read-back = previous sfdt data 3. movc: read-back = ffh (blank) table 9-1: s ecurity l ock o ptions level security lock bits 1,2 security status of: security type sfst[7:5] sb1 sb2 1 sb3 1 block 1 block 0 1 000 u u u unlock unlock no security features are enabled. 2 100 p u u softlock softlock movc instructions executed from external program memory are dis- abled from fetching code bytes from internal memory, ea# is sampled and latched on reset, and further pro- gramming of the flash is disabled. 3 011 101 u p p u p p hard lock hard lock level 2 plus verify disabled, both blocks locked. 010 u p u softlock softlock level 2 plus verify disabled. code in block 1 may program block 0 and vice versa. 110 001 p u p u u p hard lock softlock level 2 plus verify disabled. code in block 1 may program block 0. 4 111 p p p hard lock hard lock same as level 3 hard lock/hard lock, but mcu will start code execution from the internal memory regardless of ea#. t9-1.0 1255 1. p = programmed (bit logic state = 0), u = unprogrammed (bit logic state = 1). 2. sfst[7:5] = security lock status bits (sb1_i, sb2_i, sb3_i)
62 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 9-2: s ecurity l ock a ccess t able level sfst[7:5] source address 1 target address 2 byte-verify allowed movc allowed external host 3 iap 516rd2 5xrd2 4 111b (hard lock on both blocks) block 0/1 block 0/1 n n y y external n/a n/a n y external block 0/1 n n n n external n/a n/a n y 3 011b/101b (hard lock on both blocks) block 0/1 block 0/1 n n y y external n/a n/a n y external block 0/1 n n n n external n/a n/a y y 001b/110b (block 0 = softlock, block 1 = hard lock) block 0 block 0 n n y y block 1 n n n n external n/a n/a n y block 1 block 0 n y y y block 1 n n y y external n/a n/a n y external block 0/1 n n n n external n/a n/a y y 010b (softlock on both blocks) block 0 block 0 n n y y block 1 n y y y external n/a n/a n y block 1 block 0 n y y y block 1 n n y y external n/a n/a n y external block 0/1 n n n n external n/a n/a y y 2 100b (softlock on both blocks) block 0 block 0 y n y y block 1 y y y y external n/a n/a n y block 1 block 0 y y y y block 1 y n y y external n/a n/a n y external block 0/1 y n n n external n/a n/a y y 1 000b (unlock) block 0 block 0 y n y y block 1 y y y y external n/a n/a n y block 1 block 0 y y y y block 1 y n y y external n/a n/a n y external block 0/1 y y n y external n/a n/a y y t9-2.0 1255 1. location of movc or iap instruction 2. target address is the location of the byte being read 3. external host byte-verify access does not depend on a source address.
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 63 ?2004 silicon storage technology, inc. s71255-00-000 3/04 10.0 reset a system reset initializes the mcu and begins program execution at program memory location 0000h. the reset input for the device is the rst pin. in order to reset the device, a logic level high must be applied to the rst pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. ale, psen# are weakly pulled high dur- ing reset. during reset, ale and psen# output a high level in order to perform a proper reset. this level must not be affected by external element. a system reset will not affect the 1 kbyte of on-chip ram while the device is running, however, the contents of the on-chip ram during power up are indeterminate. following reset, all special function registers (sfr) return to their reset values outlined in tables 3-7 to 3-11. 10.1 power-on reset at initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algo- rithm has weakly pulled all pins high. powering up the device without a valid reset could cause the mcu to start executing instructions from an indeterminate location. such undefined states may inadvertently cor- rupt the code in the flash. when power is applied to the device, the rst pin must be held high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. an exam- ple of a method to extend the rst signal is to implement a rc circuit by connecting the rst pin to v dd through a 10 f capacitor and to v ss through an 8.2k ? resistor as shown in figure 10-1. note that if an rc circuit is being used, provisions should be made to ensure the v dd rise time does not exceed 1 millisecond and the oscillator start- up time does not exceed 10 milliseconds. for a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. this method maintains the necessary relationship between v dd and rst to avoid programming at an indeterminate location, which may cause corruption in the code of the flash. the power-on detection is designed to work as power up initially, before the voltage reaches the brown-out detection level. the pof flag in the pcon register is set to indicate an initial power up condi- tion. the pof flag will remain active until cleared by soft- ware. please refer to section 3.5, pcon register definition for detail information. for more information on system level design techniques, please review the design considerations for the sst flashflex51 family microcontroller application note. figure 10-1: p ower - on r eset c ircuit 10.2 software reset the software reset is executed by changing sfcf[1] (swr) from ?0? to ?1?. a software reset will reset the pro- gram counter to address 0000h. all sfr registers will be set to their reset values, except sfcf[1] (swr), wdtc[2] (wdts), and ram data will not be altered. 10.3 brown-out detection reset the device includes a brown-out detection circuit to protect the system from severed supplied voltage v dd fluctuations. sst89e5xxrd2 internal brown-out detection threshold is 3.85v, sst89v5xxrd2 brown-out detection threshold is 2.35v. for brown-out voltage parameters, please refer to tables 14-6 and 14-7. when v dd drops below this voltage threshold, the brown- out detector triggers the circuit to generate a brown-out interrupt but the cpu still runs until the supplied voltage returns to the brown-out detection voltage v bod . the default operation for a brown-out detection is to cause a processor reset. v dd must stay below v bod at least four oscillator clock peri- ods before the brown-out detection circuit will respond. brown-out interrupt can be enabled by setting the ebo bit in iea register (address e8h, bit 3). if ebo bit is set and a brown-out condition occurs, a brown-out interrupt will be generated to execute the program at location 004bh. it is required that the ebo bit be cleared by software after the brown-out interrupt is serviced. clearing ebo bit when the brown-out condition is active will properly reset the device. if brown-out interrupt is not enabled, a brown-out condition will reset the program to resume execution at location 0000h. 1255 f30.0 v dd v dd 10f + - 8.2k sst89e/v5xxrd2 rst xtal2 xtal1 c 1 c 2
64 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 11.0 interrupts 11.1 interrupt priority and polling sequence the device supports eight interrupt sources under a four level priority scheme. table 11-1 summarizes the polling sequence of the supported interrupts. note that the spi serial interface and the uart share the same interrupt vector. (see figure 11-1) table 11-1: i nterrupt p olling s equence description interrupt flag vector address interrupt enable interrupt priority service priority wake-up power-down ext. int0 ie0 0003h ex0 px0/h 1(highest) yes brown-out - 004bh ebo pbo/h 2 no t0 tf0 000bh et0 pt0/h 3 no ext. int1 ie1 0013h ex1 px1/h 4 yes t1 tf1 001bh et1 pt1/h 5 no pca cf/ccfn 0033h ec ppch 6 no ext. int. 2 ie2 003bh ex2 px2/h 7 no ext. int. 3 ie3 0043h ex3 px3/h 8 no uart/spi ti/ri/spif 0023h es ps/h 9 no t2 tf2, exf2 002bh et2 pt2/h 10 no t11-1.0 1255
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 65 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 11-1: i nterrupt s tructure interrupt polling sequence ie1 int1# individual enables tf1 tf0 ri 0 1 ie0 global disable highest priority interrupt lowest priority interrupt it0 it1 int0# ie & iea registers ip/iph/ipa/ipah registers 0 1 tf2 exf2 1255 f31.0 ti spie spif bof cf ecf ccfn eccfn ie2 it2 int2# 0 1 ie3 it3 int3# 0 1
66 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 12.0 power-saving modes the device provides two power saving modes of operation for applications where power consumption is critical. the two modes are idle and power-down, see table 12-1. 12.1 idle mode idle mode is entered setting the idl bit in the pcon regis- ter. in idle mode, the program counter (pc) is stopped. the system clock continues to run and all interrupts and periph- erals remain active. the on-chip ram and the special func- tion registers hold their data during this mode. the device exits idle mode through either a system inter- rupt or a hardware reset. exiting idle mode via system interrupt, the start of the interrupt clears the idl bit and exits idle mode. after exit the interrupt service routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. a hardware reset starts the device similar to a power-on reset. 12.2 power-down mode the power-down mode is entered by setting the pd bit in the pcon register. in the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. sram contents are retained during power- down, the minimum v dd level is 2.0v. the device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. the start of the interrupt clears the pd bit and exits power-down. holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. upon interrupt signal being restored to logic v ih, the first instruc- tion of the interrupt service routine will execute. a hardware reset starts the device similar to power-on reset. to exit properly out of power-down, the reset or external interrupt should not be executed before the v dd line is restored to its normal operating voltage. be sure to hold v dd voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). table 12-1: p ower s aving m odes mode initiated by state of mcu exited by idle mode software (set idl bit in pcon) mov pcon, #01h; clk is running. interrupts, serial port and tim- ers/counters are active. pro- gram counter is stopped. ale and psen# signals at a high level during idle. all registers remain unchanged. enabled interrupt or hardware reset. start of interrupt clears idl bit and exits idle mode, after the isr reti instruction, program resumes execu- tion beginning at the instruction follow- ing the one that invoked idle mode. a user could consider placing two or three nop instructions after the instruction that invokes idle mode to eliminate any problems. a hardware reset restarts the device similar to a power-on reset. power-down mode software (set pd bit in pcon) mov pcon, #02h; clk is stopped. on-chip sram and sfr data is main- tained. ale and psen# sig- nals at a low level during power -down. external inter- rupts are only active for level sensitive interrupts, if enabled. enabled external level sensitive inter- rupt or hardware reset. start of inter- rupt clears pd bit and exits power- down mode, after the isr reti instruction program resumes execution beginning at the instruction following the one that invoked power-down mode. a user could consider placing two or three nop instructions after the instruction that invokes power-down mode to eliminate any problems. a hardware reset restarts the device sim- ilar to a power-on reset. t12-1.0 1255
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 67 ?2004 silicon storage technology, inc. s71255-00-000 3/04 13.0 system clock and clock options 13.1 clock input op tions and recom- mended capacitor values for oscillator shown in figure 13-1 are the input and output of an inter- nal inverting amplifier (xtal1, xtal2), which can be con- figured for use as an on-chip oscillator. when driving the device from an external clock source, xtal2 should be left disconnected and xtal1 should be driven. at start-up, the external oscillator may encounter a higher capacitive load at xtal1 due to interaction between the amplifier and its feedback capacitance. however, the capacitance will not exceed 15 pf once the external signal meets the v il and v ih specifications. crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one applica- tion to another. c1 and c2 should be adjusted appropri- ately for each design. table 13-1, shows the typical values for c1 and c2 vs. crystal type for various frequencies more specific information about on-chip oscillator design can be found in the flashflex51 oscillator circuit design considerations application note. 13.2 clock doubling option by default, the device runs at 12 clocks per machine cycle (x1 mode). the device has a clock doubling option to speed up to 6 clocks per machine cycle. please refer to table 13-2 for detail. clock double mode can be enabled either via the external host mode or the iap mode. please refer to table 4-1 for the external host mode enabling command and to table 4- 6 and table 4-7 for the iap mode enabling commands (when set, the edc# bit in sfst register will indicate 6 clock mode.). the clock double mode is only for doubling the inter- nal system clock and the internal flash memory, i.e. ea#=1. to access the external memory and the peripheral devices, careful consideration must be taken. also note that the crystal output (xtal2) will not be doubled. figure 13-1: o scillator c haracteristics table 13-1:r ecommended v alues for c1 and c2 by c rystal t ype crystal c1 = c2 quartz 20-30pf ceramic 40-50pf t13-1.0 1255 table 13-2: c lock d oubling f eatures device standard mode (x1) clock double mode (x2) clocks per machine cycle max. external clock frequency (mhz) clocks per machine cycle max. external clock frequency (mhz) sst89e5xxrd2 12 40 6 20 sst89v5xxrd2 12 33 6 16 t13-2.0 1255 1255 f32.0 xtal2 xtal1 v ss c 1 using the on-chip oscillator external clock drive c 2 xtal2 xtal1 v ss external oscillator signal nc
68 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 14.0 electrical specification note: this specification contains preliminary information on new products in production. the specifications are subj ect to change without notice. absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c voltage on ea# pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0 v d.c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20ns) on any other pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd +1.0v maximum i ol per i/o pins p1.5, p1.6, p1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma maximum i ol per i/o for all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ma package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5w through hole lead soldering temperature (10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. (based on package heat transfer limitations, not device power consumption. table 14-1: o perating r ange symbol description min. max unit t a ambient temperature under bias standard 0 +70 c industrial -40 +85 c v dd supply voltage sst89e5xxrd2 4.5 5.5 v sst89v5xxrd2 2.7 3.6 v f osc oscillator frequency sst89e5xxrd2 0 40 mhz sst89v5xxrd2 0 33 mhz oscillator frequency for iap sst89e5xxrd2 .25 40 mhz sst89v5xxrd2 .25 33 mhz t14-1.0 1255 table 14-2: r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t14-2.0 1255
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 69 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 14-3: ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 10 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 100 pf see figures 14-8 and 14-10 t14-3.0 1255 table 14-4: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t14-4.0 1255 table 14-5: p in i mpedance (v dd =3.3v, ta=25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 15 pf c in 1 input capacitance v in = 0v 12 pf l pin 2 2. refer to pci spec. pin inductance 20 nh t14-5.0 1255
70 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 14.1 dc electrical characteristics table 14-6: dc e lectrical c haracteristics for sst89e5 xx rd2 t a = -40c to +85c; v dd = 4.5-5.5v; v ss = 0v symbol parameter test conditions min max units v il input low voltage 4.5 < v dd < 5.5 -0.5 0.2v dd - 0.1 v v ih input high voltage 4.5 < v dd < 5.5 0.2v dd + 0.9 v dd + 0.5 v v ih1 input high voltage (xtal1, rst) 4.5 < v dd < 5.5 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1.5, 1.6, 1.7) v dd = 4.5v i ol = 16ma 1.0 v v ol output low voltage (ports 1, 2, 3) 1 v dd = 4.5v i ol = 100a 2 0.3 v i ol = 1.6ma 2 0.45 v i ol = 3.5ma 2 1.0 v v ol1 output low voltage (port 0, ale, psen#) 1,3 v dd = 4.5v i ol = 200a 2 0.3 v i ol = 3.2ma 2 0.45 v v oh output high voltage (ports 1, 2, 3, ale, psen#) 4 v dd = 4.5v i oh = -10a v dd - 0.3 v i oh = -30a v dd - 0.7 v i oh = -60a v dd - 1.5 v v oh1 output high voltage (port 0 in external bus mode) 4 v dd = 4.5v i oh = -200a v dd - 0.3 v i oh = -3.2ma v dd - 0.7 v v bod brown-out detection voltage 3.85 4.15 v i il logical 0 input current (ports 1, 2, 3) v in = 0.4v -75 a i tl logical 1-to-0 transition current (ports 1, 2, 3) 5 v in = 2v -650 a i li input leakage current (port 0) 0.45 < v in < v dd -0.3 10 a r rst rst pull-down resistor 40 225 k ? c io pin capacitance 6 @ 1 mhz, 25c 15 pf i dd power supply current iap mode @ 12 mhz 70 ma @ 40 mhz 88 ma active mode @ 12 mhz 23 ma @ 40 mhz 50 ma idle mode @ 12 mhz 20 ma @ 40 mhz 42 ma power-down mode (min. v dd = 2v) t a = 0c to +70c 80 a t a = -40c to +85c 90 a t14-6.0 1255
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 71 ?2004 silicon storage technology, inc. s71255-00-000 3/04 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15ma maximum i ol per 8-bit port:26ma maximum i ol total for all outputs:71ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 & 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 & 3. the noise due to external bus capacitance discharging into the port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. i n the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 3. load capacitance for port 0, ale & psen#= 100pf, load capacitance for all other outputs = 80pf. 4. capacitive loading on ports 0 & 2 may cause the v oh on ale and psen# to momentarily fall below the v dd - 0.7 specification when the address bits are stabilizing. 5. pins of ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. 6. pin capacitance is characterized but not tested. ea# is 25pf (max).
72 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 14-7: dc e lectrical c haracteristics for sst89v5 xx rd2 t a = -40c to +85c; v dd = 2.7-3.6v; v ss = 0v symbol parameter test conditions min max units v il input low voltage 2.7 < v dd < 3.6 -0.5 0.7 v v ih input high voltage 2.7 < v dd < 3.6 0.2v dd + 0.9 v dd + 0.5 v v ih1 input high voltage (xtal1, rst) 2.7 < v dd < 3.6 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1.5, 1.6, 1.7) v dd = 2.7v i ol = 16ma 1.0 v v ol output low voltage (ports 1, 2, 3) 1 v dd = 2.7v i ol = 100a 2 0.3 v i ol = 1.6ma 2 0.45 v i ol = 3.5ma 2 1.0 v v ol1 output low voltage (port 0, ale, psen#) 1,3 v dd = 2.7v i ol = 200a 2 0.3 v i ol = 3.2ma 2 0.45 v v oh output high voltage (ports 1, 2, 3, ale, psen#) 4 v dd = 2.7v i oh = -10a v dd - 0.3 v i oh = -30a v dd - 0.7 v i oh = -60a v dd - 1.5 v v oh1 output high voltage (port 0 in external bus mode) 4 v dd = 2.7v i oh = -200a v dd - 0.3 v i oh = -3.2ma v dd - 0.7 v v bod brown-out detection voltage 2.35 2.55 v i il logical 0 input current (ports 1, 2, 3) v in = 0.4v -75 a i tl logical 1-to-0 transition current (ports 1, 2, 3) 5 v in = 2v -650 a i li input leakage current (port 0) 0.45 < v in < v dd -0.3 10 a r rst rst pull-down resistor 225 k ? c io pin capacitance 6 @ 1 mhz, 25c 15 pf i dd power supply current iap mode @ 12 mhz 40 ma @ 33 mhz 47 ma active mode @ 12 mhz 11.5 ma @ 33 mhz 30 ma idle mode @ 12 mhz 8.5 ma @ 33 mhz 21 ma power-down mode (min. v dd = 2v) t a = 0c to +70c 45 a t a = -40c to +85c 55 a t14-7.0 1255 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15ma maximum i ol per 8-bit port: 26ma maximum i ol total for all outputs: 71ma if i ol exceeds the test condition, v ol may exceed the related specification. pins ar e not guaranteed to sink current greater than the listed test conditions.
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 73 ?2004 silicon storage technology, inc. s71255-00-000 3/04 2. capacitive loading on ports 0 & 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 & 3. the noise due to external bus capacitance discharging into the port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. i n the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 3. load capacitance for port 0, ale & psen#= 100pf, load capacitance for all other outputs = 80pf. 4. capacitive loading on ports 0 & 2 may cause the v oh on ale and psen# to momentarily fall below the v dd - 0.7 specification when the address bits are stabilizing. 5. pins of ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. 6. pin capacitance is characterized but not tested. ea# is 25pf (max).
74 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-1: i dd vs . f requency for 3v sst89v5 xx rd2 figure 14-2: i dd vs . f requency for 5v sst89e5 xx rd2 30 25 20 15 10 5 0 5101520253035 i dd (ma) internal clock frequency (mhz) maximum idle i dd typical idle i dd maximum active i dd typical active i dd 1255 f33.0 50 40 30 20 10 0 510152025303540 i dd (ma) internal clock frequency (mhz) 1255 f34.0 maximum idle i dd typical idle i dd maximum active i dd typical active i dd
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 75 ?2004 silicon storage technology, inc. s71255-00-000 3/04 14.2 ac electrical characteristics ac characteristics: (over operating conditions: load capacitance for port 0, ale#, and psen# = 100pf; load capacitance for all other outputs = 80pf) table 14-8: ac e lectrical c haracteristics (1 of 2) t a = -40c to +85c, v dd = 2.7-3.6v@33mh z , 4.5-5.5v@40mh z , v ss = 0v symbol parameter oscillator units 33 mhz (x1 mode) 16 mhz (x2 mode) 1 40 mhz (x1 mode) 20 mhz (x2 mode) 1 variable min max min max min max 1/t clcl x1 mode oscillator frequency 033040 0 40 mhz 1/2t clcl x2 mode oscillator frequency 016020 0 20 mhz t lhll ale pulse width 46 35 2t clcl - 15 ns t avll address valid to ale low 5t clcl - 25 (3v) ns 10 t clcl - 15 (5v) ns t llax address hold after ale low 5t clcl - 25 (3v) ns 10 t clcl - 15 (5v) ns t lliv ale low to valid instr in 56 4t clcl - 65 (3v) ns 55 4t clcl - 45 (5v) ns t llpl ale low to psen# low 5t clcl - 25 (3v) ns 10 t clcl - 15 (5v) ns t plph psen# pulse width 66 60 3t clcl - 25 (3v) 3t clcl - 15 (5v) ns t pliv psen# low to valid instr in 35 3t clcl - 55 (3v) ns 25 3t clcl - 50 (5v) ns t pxix input instr hold after psen# 0ns t pxiz input instr float after psen# 25 t clcl - 5 (3v) ns 10 t clcl - 15 (5v) ns t pxav psen# to address valid 22 17 t clcl - 8 ns t aviv address to valid instr in 72 5t clcl - 80 (3v) ns 65 5t clcl - 60 (5v) ns t plaz psen# low to address float 10 10 10 ns t rlrh rd# pulse width 142 120 6t clcl - 40 (3v) 6t clcl - 30 (5v) ns t wlwh write pulse width (we#) 142 120 6t clcl - 40 (3v) 6t clcl - 30 (5v) ns t rldv rd# low to valid data in 62 5t clcl - 90 (3v) ns 75 5t clcl - 50 (5v) ns t rhdx data hold after rd# 00 0 ns t rhdz data float after rd# 36 2t clcl - 25 (3v) ns 38 2t clcl - 12 (5v) ns t lldv ale low to valid data in 152 8t clcl - 90 (3v) ns 150 8t clcl - 50 (5v) ns t avdv address to valid data in 183 9t clcl - 90 (3v) ns 150 9t clcl - 75 (5v) ns t llwl ale low to rd# or wr# low 66 116 60 90 3t clcl - 25 (3v) 3t clcl - 15 (5v) 3t clcl + 25 (3v) 3t clcl + 15 (5v) ns t avwl address to rd# or wr# low 46 4t clcl - 75 (3v) ns 70 4t clcl - 30 (5v) ns
76 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 explanation of symbols each timing symbol has 5 characters. the first character is always a ?t? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. for example: t avll = time from address valid to ale low t llpl = time from ale low to psen# low t whqx data hold after wr# 3t clcl - 27 (3v) ns 5t clcl - 20 (5v) ns t qvwh data valid to wr# high 142 7t clcl - 70 (3v) ns 125 7t clcl - 50 (5v) ns t qvwx data valid to wr# high to low transition 10 5 t clcl - 20 ns t rlaz rd# low to address float 0 0 0 ns t whlh rd# to wr# high to ale high 5 55 t clcl - 25 (3v) t clcl + 25 (3v) ns 10 40 t clcl - 15 (5v) t clcl + 15 (5v) ns t14-8.0 1255 1. calculated values are for x1 mode only a: address q: output data c: clock r: rd# signal d: input data t: time h: logic level high v: valid i: instruction (program memory contents) w: wr# signal l: logic level low or ale x: no longer a valid logic level p: psen# z: high impedance (float) table 14-8: ac e lectrical c haracteristics (c ontinued ) (2 of 2) t a = -40c to +85c, v dd = 2.7-3.6v@33mh z , 4.5-5.5v@40mh z , v ss = 0v symbol parameter oscillator units 33 mhz (x1 mode) 16 mhz (x2 mode) 1 40 mhz (x1 mode) 20 mhz (x2 mode) 1 variable min max min max min max
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 77 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-3: e xternal p rogram m emory r ead c ycle figure 14-4: e xternal d ata m emory r ead c ycle 1255 f35.0 port 2 port 0 psen# ale a0 - a7 t llax t plaz t pxiz t llpl t aviv t avll t pxix t lhll t lliv t pliv t plph instr in a8 - a15 a8 - a15 a0 - a7 t pxav 1255 f36.0 port 2 port 0 rd# psen# ale t lhll p2[7:0] or a8-a15 from dph a0-a7 from ri or dpl t avdv t avwl data in instr in t rlaz t avll t llax t llwl t lldv t rlrh t rldv t rhdz t whlh t rhdx a8-a15 from pch a0-a7 from pcl
78 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-5: e xternal d ata m emory w rite c ycle figure 14-6: e xternal c lock d rive w aveform table 14-9: e xternal c lock d rive symbol parameter oscillator units 12mhz 40mhz variable minmaxminmax min max 1/t clcl oscillator frequency 0 40 mhz t clcl 83 25 ns t chcx high time 8.75 0.35t clcl 0.65t clcl ns t clcx low time 8.75 0.35t clcl 0.65t clcl ns t clch rise time 20 10 ns t chcl fall time 20 10 ns t14-9.0 1255 1255 f37.0 port 2 port 0 wr# psen# ale t lhll p2[7:0] or a8-a15 from dph a0-a7 from ri or dpl data out instr in t avll t avwl t llwl t llax t wlwh t qvwh t whqx t qvwx t whlh a8-a15 from pch a0-a7 from pcl 0.2 v dd - 0.1 0.45 v t chcl t clcl t clch t clcx t chcx 0.7v dd v dd - 0.5 1255 f38.0
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 79 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-7: s hift r egister m ode t iming w aveforms figure 14-8: ac t esting i nput /o utput t est w aveform figure 14-9: f loat w aveform table 14-10: s erial p ort t iming symbol parameter oscillator units 12mhz 40mhz variable min max min max min max t xlxl serial port clock cycle time 1.0 0.3 12t clcl s t qvxh output data setup to clock rising edge 700 117 10t clcl - 133 ns t xhqx output data hold after clock rising edge 50 2t clcl - 117 ns 02t clcl - 50 ns t xhdx input data hold after clock rising edge 0 0 0 ns t xhdv clock rising edge to input data valid 700 117 10t clcl - 133 ns t14-10.0 1255 1255 f39.0 ale 0 instruction clock output data write to sbuf valid valid valid valid valid valid valid valid input data clear ri 01 2 34 567 t xlxl t qvxh t xhqx t xhdv t xhdx set ti set r i 1 2 3 4 5 6 7 8 v lt ac inputs during testing are driven at v iht (v dd -0.5v) for logic "1" and v ilt (0.45v) for a logic "0". measurement reference points for inputs and outputs are at v ht (0.2v dd + 0.9) and v lt (0.2v dd - 0.1) v ht v iht v ilt 1255 f40.0 note: v ht - v high test v lt - v low test v iht -v input high test v ilt - v input low test for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh = 20ma. v load +0.1v v load -0.1v v oh -0.1v timing reference points v ol +0.1v v load 1255 f41.0
80 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-10: a t est l oad e xample figure 14-11: i dd t est c ondition , a ctive m ode figure 14-12: i dd t est c ondition , i dle m ode figure 14-13: i dd t est c ondition , p ower - down m ode 1255 f42.0 to tester to dut c l v dd v dd v dd v dd p0 ea# rst xtal2 (nc) clock signal all other pins disconnected sst89x5xxrd2 xtal1 1255 f43.0 v ss i dd v dd v dd v dd p0 ea# rst xtal2 (nc) clock signal all other pins disconnected xtal1 1255 f45.0 v ss i dd sst89x5xxrd2 v dd v dd v dd p0 ea# rst xtal2 (nc) all other pins disconnected xtal1 1255 f44.0 v ss i dd sst89x5xxrd2 v dd = 2v
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 81 ?2004 silicon storage technology, inc. s71255-00-000 3/04 table 14-11: e xternal m ode f lash m emory p rogramming /v erification p arameters 1 parameter 2,3 symbol min max units reset setup time t su 3s read-id command width t rd 1 s psen# setup time t es 40 s address, command, data setup time t ads 0ns chip-erase time t ce 150 ms block-erase time t be 100 ms sector-erase time t se 30 ms program setup time t prog 1.2 s address, command, data hold t dh 0ns byte-program time 4 t pb 50 s select-block program time t psb 500 ns re-map or security bit program time t ps 80 s verify command delay time t oa 50 ns verify high order address delay time t aha 50 ns verify low order address delay time t ala 50 ns t14-11.0 1255 1. for iap operations, the program execution overhead must be added to the above timing parameters. 2. program and erase times will scale inversel y proportional to programming clock frequency. 3. all timing measurements are from the 50% of the input to 50% of the output. 4. each byte must be erased before programming.
82 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 14.3 flash memory programming timing diagrams with external host mode figure 14-14: r ead -id reads chip signature and identification registers at the addressed location. figure 14-15: s elect -b lock 1 / s elect -b lock 0 (f or sst89e516rd2/sst89v516rd2 only ) enables the selection of either of the flash memory blocks prior to issuing a byte-verify, block-erase, sector- erase, or byte-program. 1255 f46.0 0030h t su t es rst psen# ale/prog# ea# p3[5:4] ,p2[5:0] ,p1 p2[7:6] ,p3[7:6] p0 0000b t rd bfh 0031h 0000b t rd device id device id = see table 4-3, "product identification" rst psen# ale/prog# ea# p3[3] p3[5:4], p2[5:0] a5h/55h t psb t prog t ads 1255 f47.0 p3[7:6], p2[7:6] 1001b t dh t su t es
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 83 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-16: c hip -e rase erases both flash memory blocks. security lock is ignored and the security bits are erased too. figure 14-17: b lock -e rase for sst89e516rd2/sst89v516rd2 erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] 0001b t ce t prog t ads 1255 f48.0 t es t su t dh ea# rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] 1101b t be t prog t su t ads 1255 f49.0 t es t dh ea#
84 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-18: b lock -e rase for sst89e5 x rd2/sst89v5 x rd2 erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. figure 14-19: s ector -e rase erases the addressed sector if the security lock is not activated on that flash memory block. rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] p3[5:4], p2[5:0] 1101b ah t be t prog t su t ads 1255 f50.0 t es t dh ea# rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] p3[5:4], p2[5:0] 1011b ah t se t prog t ads 1255 f51.0 p1 al t dh t su t es ea#
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 85 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-20: b yte -p rogram programs the addressed code byte if the byte location has been successfully erased and not yet programmed. byte-program operation is only allowed when the security lock is not activated on that flash memory block. figure 14-21: p rog -sb1 / p rog -sb2 / p rog -sb3 programs the security bits sb1, sb2 and sb3 respectively. only a chip-erase will erase a programmed security bit. rst psen# ale/prog# ea# p3[3] p3[5:4], p2[5:0] p1 ah al t pb t prog t ads 1255 f52.0 p0 p3[7:6], p2[7:6] di 1110b t dh t su t es rst psen# ale/prog# ea# p3[3] t ps t prog t ads 1255 f53.0 p3[7:6], p2[7:6] 1111b / 0011b / 0101b t dh t su t es
86 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 figure 14-22: p rog -sc0 / p rog -sc1 programs the start-up configuration bit sc0/sc1. only a chip-erase will erase a programmed sc0/sc1 bit. prog-sc1 applies to sst89e5xrd2/sst89v5xrd2 only. figure 14-23: b yte -v erify reads the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. rst psen# ale/prog# ea# p3[3] p3[5:4], p2[5:0] 5ah / aah t ps t prog t ads 1255 f54.0 p3[7:6], p2[7:6] 1001b t dh t su t es 1255 f55.0 p3[5:4], p2[5:0] al do 1100b p3[7:6], p2[7:6] t su rst psen# ale/prog# ea# p0 p1 t ala t oa t aha ah t es
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 87 ?2004 silicon storage technology, inc. s71255-00-000 3/04 15.0 product ordering information 15.1 valid combinations valid combinations for sst89e52rd2 sst89e52rd2-40-c-pi sst89e52rd2-40-c-nj sst89e52rd2-40-c-tqj sst89e52rd2-40-c-pie sst89e52rd2-40-c-nje sst89e52rd2-40-c-tqje sst89e52rd2-40-i-pi sst89e52rd2-40-i-nj sst89e52rd2-40-i-tqj sst89e52rd2-40-i-pie sst89e52rd2-40-i-nje sst89e52rd2-40-i-tqje valid combinations for sst89v52rd2 sst89v52rd2-33-c-pi sst89v52rd2-33-c-nj sst89v52rd2-33-c-tqj sst89v52rd2-33-c-pie sst89v52rd2-33-c-nje sst89v52rd2-33-c-tqje sst89v52rd2-33-i-pi sst89v52rd2-33-i-nj sst89v52rd2-33-i-tqj sst89v52rd2-33-i-pie sst89v52rd2-33-i-nje sst89v52rd2-33-i-tqje device speed suffix1 suffix2 sst89 x 5xx rd2 - xx -x -x x package modifier i = 40 pins j = 44 pins package type p = pdip n = plcc tq = tqfp operation temperature c = commercial = 0c to +70c i = industrial = -40c to +85c operating frequency 33 = 0-33mhz 40 = 0-40mhz feature set and flash memory size 52rd2 = c52 feature set + 8(16) kbyte 54rd2 = c52 feature set + 16(32) kbyte 58rd2 = c52 feature set + 32(40) kbyte 516rd2 = c52 feature set + 64(72) kbyte note: number in parenthesis includes an additional 8 kbyte flash which can be enabled. voltage range e = 4.5-5.5v v = 2.7-3.6v product series 89 = c51 core
88 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 valid combinations for sst89e54rd2 sst89e54rd2-40-c-pi sst89e54rd2-40-c-nj sst89e54rd2-40-c-tqj sst89e54rd2-40-c-pie sst89e54rd2-40-c-nje sst89e54rd2-40-c-tqje sst89e54rd2-40-i-pi sst89e54rd2-40-i-nj sst89e54rd2-40-i-tqj sst89e54rd2-40-i-pie sst89e54rd2-40-i-nje sst89e54rd2-40-i-tqje valid combinations for sst89v54rd2 sst89v54rd2-33-c-pi sst89v54rd2-33-c-nj sst89v54rd2-33-c-tqj sst89v54rd2-33-c-pie sst89v54rd2-33-c-nje sst89v54rd2-33-c-tqje sst89v54rd2-33-i-pi sst89v54rd2-33-i-nj sst89v54rd2-33-i-tqj sst89v54rd2-33-i-pie sst89v54rd2-33-i-nje sst89v54rd2-33-i-tqje valid combinations for sst89e58rd2 sst89e58rd2-40-c-pi sst89e58rd2-40-c-nj sst89e58rd2-40-c-tqj sst89e58rd2-40-c-pie sst89e58rd2-40-c-nje sst89e58rd2-40-c-tqje sst89e58rd2-40-i-pi sst89e58rd2-40-i-nj sst89e58rd2-40-i-tqj sst89e58rd2-40-i-pie sst89e58rd2-40-i-nje sst89e58rd2-40-i-tqje valid combinations for sst89v58rd2 sst89v58rd2-33-c-pi sst89v58rd2-33-c-nj sst89v58rd2-33-c-tqj sst89v58rd2-33-c-pie sst89v58rd2-33-c-nje sst89v58rd2-33-c-tqje sst89v58rd2-33-i-pi sst89v58rd2-33-i-nj sst89v58rd2-33-i-tqj sst89v58rd2-33-i-pie sst89v58rd2-33-i-nje sst89v58rd2-33-i-tqje valid combinations for sst89e516rd2 sst89e516rd2-40-c-pi sst89e516rd2-40-c-nj sst89e516rd2-40-c-tqj sst89e516rd2-40-c-pie sst89e516rd2-40-c-nje sst89e516rd2-40-c-tqje sst89e516rd2-40-i-pi sst89e516rd2-40-i-nj sst89e516rd2-40-i-tqj sst89e516rd2-40-i-pie sst89e516rd2-40-i-nje sst89e516rd2-40-i-tqje valid combinations for sst89v516rd2 sst89v516rd2-33-c-pi sst89v516rd2-33-c-nj sst89v516rd2-33-c-tqj sst89v516rd2-33-c-pie sst89v516rd2-33-c-nje sst89v516rd2-33-c-tqje sst89v516rd2-33-i-pi sst89v516rd2-33-i-nj sst89v516rd2-33-i-tqj sst89v516rd2-33-i-pie sst89v516rd2-33-i-nje sst89v516rd2-33-i-tqje note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations.
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 89 ?2004 silicon storage technology, inc. s71255-00-000 3/04 16.0 packaging diagrams 40- pin p lastic d ual i n - line p ins (pdip) sst p ackage c ode : pi 40-pdip-pi-7 pin #1 identifier c l 40 1 base plane seating plane .220 max. 12? 4 places .600 bsc .100 bsc .100 ? .200 .015 .022 .045 .055 .063 .090 .015 min. .065 .075 2.020 2.070 .008 .012 0? 15? .600 .625 .530 .557 note: 1. complies with jedec publication 95 ms-011 ac dimensions (except as noted), although some dimensions may be more strin gent. ? = jedec min is .115; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches.
90 preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 ?2004 silicon storage technology, inc. s71255-00-000 3/04 44- lead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nj .025 .045 .013 .021 .590 .630 .100 .112 .020 min. .165 .180 top view side view bottom view 144 .026 .032 .500 ref. 44-plcc-nj-7 note: 1. complies with jedec publication 95 ms-018 ac dimensions (except as noted), although some dimensions may be more strin gent. ? = jedec min is .650; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc. .050 bsc. .026 .032 .042 .056 .646 ? .656 .042 .048 .042 .048 optional pin #1 identifier .646 ? .656 .685 .695 .685 .695 .020 r. max. .147 .158 r. x45?
preliminary specifications flashflex51 mcu sst89e52rd2 / sst89e54rd2 / sst89e58rd2 / sst89e516rd2 sst89v52rd2 / sst89v54rd2 / sst89v58rd2 / sst89v516rd2 91 ?2004 silicon storage technology, inc. s71255-00-000 3/04 44- lead t hin q uad f lat p ack (tqfp) sst p ackage c ode : tqj table 16-1: r evision h istory number description date 00 initial release mar 2004 note: 1. complies with jedec publication 95 ms-026 acb dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (0.05) mm. 4. package body dimensions do not include mold flash. maximum allowable mold flash is .25mm. 44-tqfp-tqj-7 .45 .75 10.00 0.10 12.00 0.25 1.00 ref 0?- 7? 1 11 33 23 12 22 44 34 1.2 max. .95 1.05 .05 .15 pin #1 identifier .30 .45 .09 .20 .80 bsc 12.00 0.25 10.00 0.10 1mm silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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